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參數(shù)資料
| 型號(hào)： | STM32W108HBU7 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-40 |
| 文件頁(yè)數(shù)： | 44/198頁(yè) |
| 文件大?。?/td> | 2871K |
| 代理商： | STM32W108HBU7 |
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General-purpose timers
STM32W108CB, STM32W108HB
138/198
Doc ID 16252 Rev 3
Bit 10 TIM_OC2FE: Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0)
This bit speeds the effect of an event on the trigger in input on the OC2 output.
0: OC2 behaves normally depending on the counter and TIM_CCR2 values even when the
trigger is ON. The minimum delay to activate OC2 when an edge occurs on the trigger input is 5
clock cycles.
1: An active edge on the trigger input acts like a compare match on the OC2 output. OC2 is set
to the compare level independently from the result of the comparison. Delay to sample the
trigger input and to activate OC2 output is reduced to 3 clock cycles. TIM_OC2FE acts only if
the channel is configured in PWM 1 or PWM 2 mode.
Bits [15:12] TIM_IC2F: Input Capture 1 Filter. (Applies only if TIM_CC2S > 0)
This defines the frequency used to sample the TI2 input, Fsampling, and the length of the
digital filter applied to TI2. The digital filter requires N consecutive samples in the same state
before being output.
0000: Fsampling=PCLK, no filtering.
1000: Fsampling=PCLK/8, N=6.
0001: Fsampling=PCLK, N=2.
1001: Fsampling=PCLK/8, N=8.
0010: Fsampling=PCLK, N=4.
1010: Fsampling=PCLK/16, N=5.
0011: Fsampling=PCLK, N=8.
1011: Fsampling=PCLK/16, N=6.
0100: Fsampling=PCLK/2, N=6.
1100: Fsampling=PCLK/16, N=8.
0101: Fsampling=PCLK/2, N=8.
1101: Fsampling=PCLK/32, N=5.
0110: Fsampling=PCLK/4, N=6.
1110: Fsampling=PCLK/32, N=6.
0111: Fsampling=PCLK/4, N=8.
1111: Fsampling=PCLK/32, N=8.
Note: PCLK is 12 MHz when using the 24 MHz crystal oscillator, and 6 MHz using the 12 MHz
RC oscillator.
Bits [11:10] TIM_IC2PSC: Input Capture 1 Prescaler. (Applies only if TIM_CC2S > 0)
00: No prescaling, capture each time an edge is detected on the capture input.
01: Capture once every 2 events.
10: Capture once every 4 events.
11: Capture once every 6 events.
Bits [9:8] TIM_CC2S: Capture / Compare 1 Selection
This configures the channel as an output or an input. If an input, it selects the input source.
00: Channel is an output.
01: Channel is an input and is mapped to TI2.
10: Channel is an input and is mapped to TI1.
11: Channel is an input and is mapped to TRGI. This mode requires an internal trigger input
selected by the TIM_TS bit in the TIMx_SMCR register.
Note: TIM_CC2S may be written only when the channel is off (TIM_CC2E = 0 in the
TIMx_CCER register).
Bits [6:4] TIM_OC1M: Output Compare 1 Mode. (Applies only if TIM_CC1S = 0)
See TIM_OC2M description above.
Bit 3 TIM_OC1BE: Output Compare 1 Buffer Enable. (Applies only if TIM_CC1S = 0)
See TIM_OC2BE description above.
Bit 2 TIM_OC1FE: Output Compare 1 Fast Enable. (Applies only if TIM_CC1S = 0)
See TIM_OC2FE description above.
Bits [7:4] TIM_IC1F: Input Capture 1 Filter. (Applies only if TIM_CC1S > 0)
See TIM_IC2F description above.
Bits [3:2] TIM_IC1PSC: Input Capture 1 Prescaler. (Applies only if TIM_CC1S > 0)
See TIM_IC2PSC description above.
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