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| 型號(hào)： | STM32W108HBU7 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-40 |
| 文件頁(yè)數(shù)： | 43/198頁(yè) |
| 文件大?。?/td> | 2871K |
| 代理商： | STM32W108HBU7 |
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STM32W108CB, STM32W108HB
General-purpose timers
Doc ID 16252 Rev 3
137/198
10.3.5
Timer x capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0xE018 (TIM1) and 0xF018 (TIM2)
Reset value:
0x0000 0000
Timer channels can be programmed as inputs (capture mode) or outputs (compare mode).
The direction of channel y is defined by TIM_CCyS in this register.
The other bits in this register have different functions in input and in output modes. The
TIM_OC* fields only apply to a channel configured as an output (TIM_CCyS = 0), and the
TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIM_OC2M
TIM_O
C2BE
TIM_O
C2FE
TIM_CC2S
TIM_OC1M
TIM_O
C1BE
TIM_O
C1FE
TIM_CC1S
TIM_IC2F
TIM_IC2PSC
TIM_IC1F
TIM_IC1PSC
rw
Bits [14:12] TIM_OC2M: Output Compare 2 Mode. (Applies only if TIM_CC2S = 0
Define the behavior of the output reference signal OC2REF from which OC2 derives. OC2REF
is active high whereas OC2''s active level depends on the TIM_CC2P bit.
000: Frozen - The comparison between the output compare register TIMx_CCR2 and the
counter TIMx_CNT has no effect on the outputs.
001: Set OC2REF to active on match. The OC2REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2)
010: Set OC2REF to inactive on match. OC2REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2).
011: Toggle - OC2REF toggles when TIMx_CNT = TIMx_CCR2.
100: Force OC2REF inactive.
101: Force OC2REF active.
110: PWM mode 1 - In up-counting, OC2REF is active as long as TIMx_CNT < TIMx_CCR2,
otherwise OC2REF is inactive. In down-counting, OC2REF is inactive if
TIMx_CNT > TIMx_CCR2, otherwise OC2REF is active.
111: PWM mode 2 - In up-counting, OC2REF is inactive if TIMx_CNT < TIMx_CCR2, otherwise
OC2REF is active. In down-counting, OC2REF is active if TIMx_CNT > TIMx_CCR2, otherwise
it is inactive.
Note: In PWM mode 1 or 2, the OC2REF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode to
“PWM” mode.
Bit 11 TIM_OC2BE: Output Compare 2 Buffer Enable. (Applies only if TIM_CC2S = 0
0: Buffer register for TIMx_CCR2 is disabled. TIMx_CCR2 can be written at anytime, the new
value is used by the shadow register immediately.
1: Buffer register for TIMx_CCR2 is enabled. Read/write operations access the buffer register.
TIMx_CCR2 buffer value is loaded in the shadow register at each update event.
Note: The PWM mode can be used without enabling the buffer register only in one pulse mode
(TIM_OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.
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