STM32W108CB, STM32W108HB
Serial interfaces
Doc ID 16252 Rev 3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SC_RXSSEL
SC_RX
FRMB
SC_RX
FRMA
SC_RX
PARB
SC_RX
PARA
SC_RX
OVFB
SC_R
XOVF
A
SC_TX
ACTB
SC_TX
ACTA
SC_RX
ACTB
SC_RX
ACTA
r
rr
r
rr
r
Bits [12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode)
when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is
reset.
0: No count was saved because nSSEL did not deassert.
2: Buffer A's count was saved, nSSEL deasserted once.
3: Buffer B's count was saved, nSSEL deasserted once.
6: Buffer A's count was saved, nSSEL deasserted more than once.
7: Buffer B's count was saved, nSSEL deasserted more than once.
1, 4, 5: Reserved.
Bit 9 SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame error from
the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
Bit 8 SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame error from
the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
Bit 7 This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO.
It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
Bit 6 This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO.
It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
Bit 5 This bit is set when DMA receive buffer B was passed an overrun error from the receive FIFO.
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled
up. Buffer B was the next buffer to load, and when it drained the FIFO the overrun error was
passed up to the DMA and flagged with this bit. Cleared the next time buffer B is loaded and
when the receive DMA is reset.
Bit 4 This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO.
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled
up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was
passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and
when the receive DMA is reset.
Bit 3 This bit is set when DMA transmit buffer B is active.
Bit 2 This bit is set when DMA transmit buffer A is active.
Bit 1 This bit is set when DMA receive buffer B is active.
Bit 0 This bit is set when DMA receive buffer A is active.