參數(shù)資料
型號(hào)： T431616D-5S
廠商： Electronic Theatre Controls, Inc.
英文描述： 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述： 100萬(wàn)× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM
文件頁(yè)數(shù)： 13/74頁(yè)
文件大?。?/td> 781K
代理商： T431616D-5S
TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 20
Publication Date: FEB. 2007
to change products or specifications without notice.
Revision: A
LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
3.3V
1.2k
87 0
30pF
Output
1.4V
50
Output
30pF
50
Z0=
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be
added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both
CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200us minimum is required. Then, it is recommended that LDQM/UDQM is held
"HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register Set command
in step 4 to stabilize the internal circuitry of the device.
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T431616D 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T431616D-5SG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6C 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6CG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6SG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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