參數(shù)資料
型號(hào)： T431616D-5S
廠商： Electronic Theatre Controls, Inc.
英文描述： 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述： 100萬(wàn)× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM
文件頁(yè)數(shù)： 8/74頁(yè)
文件大?。?/td> 781K
代理商： T431616D-5S
TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 16
Publication Date: FEB. 2007
to change products or specifications without notice.
Revision: A
14
Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent
cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is
suspended. On the other hand, when both banks are in the idle state, this command performs entry into the
PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode.
The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms)
since the command does not perform any refresh operations.
15 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing Waveforms,
CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the
subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown
mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required
when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock
cycle from the end of this command.
16
Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every word of the
input data. During a read cycle, the LDQM/UDQM functions as the controller of output buffers. LDQM/UDQM
is also used for device selection, byte selection and bus control in a memory system. LDQM controls DQ0 to
DQ7, UDQM controls DQ8 to DQ15.
相關(guān)PDF資料
PDF描述
T431616D 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616E 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T450N 0 MHz - 10000 MHz 50 ohm RF/MICROWAVE TERMINATION
T451N 0 MHz - 10000 MHz 50 ohm RF/MICROWAVE TERMINATION
T523-020.00M TCXO, CLIPPED SINE OUTPUT, 20 MHz
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T431616D-5SG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6C 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6CG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-6SG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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