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參數(shù)資料
| 型號： | T431616D-5S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 74/74頁 |
| 文件大?。?/td> | 781K |
| 代理商： | T431616D-5S |
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TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 9
Publication Date: FEB. 2007
to change products or specifications without notice.
Revision: A
4
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.)
+ burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge
function is ignored.
5
Write command
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
CLK
COM M A ND
T0
T1
T2T3
T4T5
T6T7
T8
DIN A3
NOP
WRITE A
NOP
DIN A0
DIN A1
DIN A2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
don't care
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
CLK
COM M AND
T0
T1
T2
T3
T4T5
T6T7
T8
DIN B2
NOP
WRITE A
NOP
WRITE B
NOP
DIN A0
DIN B0
DIN B1
DQ's
DIN B3
1 Clk Interval
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
相關(guān)PDF資料 |
PDF描述 |
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| T431616D | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616E | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T450N | 0 MHz - 10000 MHz 50 ohm RF/MICROWAVE TERMINATION |
| T451N | 0 MHz - 10000 MHz 50 ohm RF/MICROWAVE TERMINATION |
| T523-020.00M | TCXO, CLIPPED SINE OUTPUT, 20 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T431616D-5SG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-6C | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-6CG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-6S | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T431616D-6SG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
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