參數(shù)資料
型號: T7121-EL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 36/68頁
文件大小: 685K
代理商: T7121-EL2
36
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
* The HIFI-64 can transmit on either DXA, DXB, or both. If both pins are selected via these register bits, the same data byte is sent during the
same time slot on both pins.
Table 14. Register R7—Transmit Time-Slot Control Register
R7—B7
DXAC
(0)
R7—B6
DXBC
(0)
R7—B5
TSLT5
(0)
R7—B4
TSLT4
(0)
R7—B3
TSLT3
(0)
R7—B2
TSLT2
(0)
R7—B1
TSLT1
(0)
R7—B0
TSLT
(0)
Register
R7
Bit
Symbol
TSLT0—TSLT5
Transmitter Time Slot.
These 6 bits, representing a value from 0
to 63, coded in binary with bit 0 the LSB, define the transmit time-
slot number for transmission on the chosen pin (DXA and/or DXB).
DXBC
Transmit Data DXB Control.
When this bit is set to 1, data is
transmitted on the DXB pin (pin 17). Setting P17CTL (R5 B7) to 1
overrides the setting of DXBC.
DXAC
Transmit Data DXA Control.
When this bit is set to 1, data is
transmitted on the DXA pin (pin 19).
Name/Function
B(0—5)
R7
B6*
R7
B7*
Table 15. Register R8—Receiver Time-Slot Control Register
R8—B7
DRA/B
(0)
R8—B6
CMS
(0)
R8—B5
RSLT5
(0)
R8—B4
RSLT4
(0)
R8—B3
RSLT3
(0)
R8—B2
RSLT2
(0)
R8—B1
RSLT1
(0)
R8—B0
RSLT0
(0)
Register
R8
Bit
Symbol
Name/Function
B(0—5)
RSLT0—RSLT5
Receiver Time Slot.
These 6 bits, representing a value from 0 to 63,
coded in binary with bit 0 the LSB, define the receive time-slot number
for information received on the chosen receive data pin (DRA or DRB).
CMS
Clock Mode Select.
When set to 1, this bit allows the HIFI-64 to com-
municate with an IOM2 or GCI interface by effectively dividing the data
clock internally by two. (See the serial link interface section for details
on configuring to IOM2 interface.)
DRA/B
Receive Data on DRA or DRB.
This bit determines which pin the
HIFI-64 receiver uses to access received data. When this bit is 0,
received data is expected on the DRA pin. When this bit is set to 1,
received data is expected on the DRB pin. (This option implies
P21CTL [R5—B6] is set to 1.)
R8
B6
R8
B7
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