參數(shù)資料
型號: T7121-EL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 38/68頁
文件大?。?/td> 685K
代理商: T7121-EL2
38
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Table 17. Register R10—Transmitter Time-Slot Offset Control Register
R10—B7
DXI
(0)
R10—B6
TLBIT
(1)
R10—B5
TTSOF5
(0)
R10—B4
TTSOF4
(0)
R10—B3
TTSOF3
(0)
R10—B2
TTSOF2
(0)
R10—B1
TTSOF1
(0)
R10—B0
TTSOF0
(0)
Register
R10
Bit
Symbol
Name/Function
B(0—5)
TTSOF0—TTSOF5
Transmitter Time-Slot Offset.
The value of these 6 bits,
coded in binary with bit 0 being the LSB, specifies the number
of time slots to delay between the beginning of the first locat-
able time slot and the beginning of a new virtual TDM frame
(i.e., the time slot defined by the user as time slot 0). See Fig-
ure 5 for an example of using the TTSOF bits.
TLBIT
Transmit Least Significant Bit First.
This bit is used to con-
trol whether the least significant or most significant data bit is
transmitted first. The least significant bit of transmit data is
defined as the transmit FIFO data bit written by the host on the
AD0 pin. When TLBIT is 0, the most significant bit of data is
transmitted first, and when TLBIT is set to 1, the least signifi-
cant bit of data is transmitted first.
R10
B6
TLBIT has no meaning when not in the TDM highway mode
(i.e., HWYEN, R0—B7 = 0). Data in non-TDM highway mode is
always least significant bit first.
Transmit Data Inverted.
If this bit is set to 1, the serial data
output is inverted before transmission.
R10
B7
DXI
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