參數(shù)資料
型號: T7121-EL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 58/68頁
文件大?。?/td> 685K
代理商: T7121-EL2
58
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Timing Characteristics
(continued)
(CMS = 1, CLKXI = 1, CLKRI = 0, FSPOL = 1, RMB = TBM = 11111111)
5-5051
1. Edge of clock used to sample FS (selected by the FE bit [R0—B6]).
2. Edge of first bit transmission (see Figures 12—20).
3. The CLKXI bit (R9—B4) controls the edge on which data is transmitted, and the CLKRI bit (R9—B0) controls the edge on which received
data is sampled.
Figure 25. Timing for Concentration Highway
Table 29. Concentration Highway Timing for CMS = 1
Symbol on
Diagram
A
B
C
D
E
F
G
H
I
J
Name
Parameter
Min
Max
Unit
tDCLDCL
tFSHCKE
tCKEFSL
tCEDV
tCEDT
tCETSL
tCETST
tDVRCE
tRCEDI
tFSFS
CLKX/R Period
FS High to CLKX/R Edge Selected
FS Hold After CLKX/R Edge Selected
CLKX Edge to Data Valid
CLKX Edge to Data 3-state
CLKX Edge to
TSCA
Low
CLKX Edge to
TSCA
3-state
Receive Data Setup Time
Receive Data Hold Time
FS Period
122
50
50
0
0
25
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDCLDCL – 30
80
45
70
70
18 tDCLDCL 1024 tDCLDCL
CLKX
CLKR
TSCA
FS
(FE = 0)
DXA
AND/OR
DXB
(CLKXI = 1)
DRA
OR
DRB
(CLKRI = 0)
BIT 7
3
3
1
C
B
D
F
D
H
I
G
E
J
A
2
BIT 0
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