參數(shù)資料
型號: T7121-EL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 40/68頁
文件大小: 685K
代理商: T7121-EL2
40
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
* The octet boundary is relative to the time-slot boundary if HWYEN (R0—B7) = 1, or relative to the first receive clock edge after the receiver
has been enabled (ENR, R6—B2 = 1) if HWYEN = 0.
Table 19. Alternate Register AR11—Transparent-Mode Control Register
AR11—B7
TEST
(0)
AR11—B6
TRANS
(0)
AR11—B5
MATCH
(0)
AR11—B4
ALOCT
(0)
AR11—B3
MSTAT
(0)
AR11—B2
OCTOF2
(0)
AR11—B1
OCTOF1
(0)
AR11—B0
OCTOF0
(0)
Register
AR11
Bit
Symbol
Name/Function
B(0—2)
OCTOF0—OCTOF2
Octet Bit Offset.
Read only. These bits record the offset relative
to the octet boundary* when the receive character was matched.
The OCTOF bits are valid when MSTAT (AR11—B3) is set to 1.
These bits indicate one less than the actual offset; i.e., no offset
is 111 (byte alignment), one bit of offset is 000, etc.
Match Status.
Read only. When this bit is set to 1, the receiver
match character has been recognized. The octet offset status bits
(AR11—B[0—2]) indicate the offset relative to the octet bound-
ary* at which the receive character was matched. If no match is
being performed (MATCH AR11—B5 = 0), the MSTAT bit is set to
1 automatically when the first bit is received, and the octet offset
status bits (AR11—B[0—2]) read 000.
Frame-Sync Align.
When this bit is set to 1, the HIFI-64
searches for the receive match character (AR12) only on an octet
boundary. When this bit is 0, the HIFI-64 searches for the receive
match character in a sliding window fashion. See Table 5.
Pattern Match.
MATCH affects both the transmitter and receiver.
When this bit is set to 1, the HIFI-64 does not load data into the
receive FIFO until the receive match character programmed in
AR12 has been detected. The search for the receive match char-
acter is in a sliding window fashion if the ALOCT bit (AR11—B4)
is 0, or only on octet boundaries* if the ALOCT bit (AR11—B4) is
set to 1. When this bit is 0, the HIFI-64 loads the matched byte
and all subsequent data directly into the receive FIFO. See
Table 5.
AR11
B3
MSTAT
AR11
B4
ALOCT
AR11
B5
MATCH
On the transmit side, when this bit is set to 1, the transmitter
sends the transmit idle character programmed into AR13 when
the transmit FIFO has no user data. The default idle is to transmit
the HDLC 1s idle character (FF hexadecimal); however, any
value can be used by programming the transmit idle character
register (AR13). If this bit is 0, the transmitter sends 1s idle char-
acters when the transmit FIFO is empty.
Transparent Mode.
When this bit is set to 1, the HIFI-64 per-
forms no HDLC processing on incoming or outgoing data.
TEST.
This bit is reserved for manufacturing test purposes only.
Program to 0.
AR11
B6
TRANS
AR11
B7
TEST
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