參數(shù)資料
型號: T7121-EL2
英文描述: T7121 HDLC Interface for ISDN
中文描述: T7121的HDLC接口用于ISDN
文件頁數(shù): 46/68頁
文件大小: 685K
代理商: T7121-EL2
46
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Clock Characteristics
System Clock Input (CLK): 0 MHz—12 MHz.
Transmit Data Clock (CLKX): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz.
Receive Data Clock (CLKR): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz.
* 8.192 MHz in CMS mode (R8—B6 = 1).
Timing Characteristics
TDM Frame Timing Diagrams
The timing of the transmission or reception of the first bit relative to the frame-sync pulse depends on the configu-
ration of 3 bits: FE (R0—B5), CLKXI (R9—B4), CLKRI (R9—B0). The timing diagrams below illustrate different
configurations of FE, CLKXI, and CLKRI.
5-5038
Figure 12. FE = 0, CLKXI = 0, CLKRI = 0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR
FIRST BIT TRANSMITTED
CLKX/CLKR
FS
(FE = 0)
DXA/B
(CLKXI = 0)
TSCA
DRA/B
(CLKRI = 0)
3-STATE
FIRST BIT SAMPLED
DON'T CARE
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