參數資料
型號： T7121-EL2
英文描述： T7121 HDLC Interface for ISDN
中文描述： T7121的HDLC接口用于ISDN
文件頁數： 43/68頁
文件大小： 685K
代理商： T7121-EL2
Lucent Technologies Inc.
43
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
* The first occurrence of an unmasked interrupt causes the INT pin to transition. The INT pin remains active until the interrupt is acknowledged
by a read of register 15. Additional unmasked interrupts occurring before the read of register 15 do
not
cause a new transition of the INT pin,
but are reported in register 15 when it is read.
Table 24. Register R14—Interrupt Mask Register
R14—B7
TBCRC
(0)
R14—B6
RIIE
(0)
R14—B5
ROVIE
(0)
R14—B4
REOFIE
(0)
R14—B3
RFIE
(0)
R14—B2
UNDIE
(0)
R14—B1
TEIE
(0)
R14—B0
TDIE
(0)
Register
R14
Bit
B0
Symbol
TDIE
Name/Function
Transmit-Done Interrupt Enable.
When this interrupt enable bit is set, an
INT pin transition* is generated after the last bit of the closing flag or abort
sequence is sent. In the transparent mode (TRANS, AR11—B6 = 1), an INT
pin transition is generated when the transmit FIFO is completely empty.
TDIE is cleared upon reset.
Transmitter-Empty Interrupt Enable.
When this interrupt-enable bit is set,
an INT pin transition is generated when the transmit FIFO has reached the
programmed empty level (see Register 1). TEIE is cleared upon reset.
Underrun Interrupt Enable.
When this interrupt-enable bit is set, an INT
pin transition is generated when the transmit FIFO has underrun. UNDIE is
cleared upon reset. UNDIE is not used in transparent mode.
Receiver-Full Interrupt Enable.
When this interrupt-enable bit is set, an
INT pin transition is generated when the receive FIFO has reached the pro-
grammed full level (see Register 5). RFIE is cleared upon reset.
Receive End-of-Frame Interrupt Enable.
When this interrupt-enable bit is
set, an INT pin transition is generated when an end-of-frame is detected by
the HDLC receiver. REOFIE is cleared upon reset. REOFIE is not used in
transparent mode.
Receiver Overrun Interrupt Enable.
When this interrupt-enable bit is set,
an INT pin transition is generated when the receive FIFO overruns. ROVIE
is cleared upon reset.
Receiver Idle-Interrupt Enable.
When this interrupt-enable bit is set, an
INT pin transition is generated when the receiver enters the idle state. RIIE
is cleared upon reset. RIIE is not used in transparent mode.
Transmit Bad CRC.
Setting this bit to 1 forces bad CRCs to be sent on all
transmitted frames (for test purposes) until the TBCRC bit is cleared to 0.
R14
B1
TEIE
R14
B2
UNDIE
R14
B3
RFIE
R14
B4
REOFIE
R14
B5
ROVIE
R14
B6
RIIE
R14
B7
TBCRC
相關PDF資料
PDF描述
T7121-PL2 T7121 HDLC Interface for ISDN
T7121 HDLC Interface for ISDN (HIFI-64)(應用于ISDN的HDLC（高階數據鏈路）接口)
T7502 T7502 Dual PCM Codec with Filters
T7503 T7503 Dual PCM Codec with Filters
T7504 T7504 and T75504 Quad PCM Codecs with Filters
相關代理商/技術參數
參數描述
T7-121F1 功能描述:撥動開關 ON OFF ON 1 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-121F5 功能描述:撥動開關 ON OFF ON 1 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-121G1 功能描述:撥動開關 (ON) OFF ON 1 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-121G5 功能描述:撥動開關 (ON) OFF ON 1 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-121H1 制造商:OTTO 功能描述:Toggle Switches OFF NONE ON 1 Pole Standard Bat Handle 制造商:OTTO Engineering Inc 功能描述:TOGGLE SWITCH 1 POLE
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*