參數(shù)資料
型號: T7121
廠商: Lineage Power
英文描述: HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC(高階數(shù)據(jù)鏈路)接口)
中文描述: 為ISDN接口的HDLC(高保真- 64)(應(yīng)用于綜合業(yè)務(wù)數(shù)字網(wǎng)的的HDLC(高階數(shù)據(jù)鏈路)接口)
文件頁數(shù): 15/68頁
文件大?。?/td> 685K
代理商: T7121
Lucent Technologies Inc.
15
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
5-5032
Note: abcdefgh are not the same as ABCDEFGH due to HDLC processing.
Figure 6. Transmission and Reception of Data LSB First
5-5033
Note: abcdefgh are not the same as ABCDEFGH due to HDLC processing.
Figure 7. Transmission and Reception of Data MSB First
a b c d e f g h
HDLC
A B C D E F G H
H G F E D C B A
TRANSMIT FIFO
TRANSMITTER HDLC
PROCESSES LSB FIRST
FIRST BIT
TRANSMITTED
TIME-SLOT DATA
MSB
BIT 7
LSB
BIT 0
MSB
BIT 7
LSB
BIT 0
DIRECTION OF TRANSMISSION
TLBIT = 1 (TRANSMIT LSB FIRST)
a b c d e f g h
HDLC
A B C D E F G H
H G F E D C B A
RECEIVE FIFO
RECEIVER HDLC
EXPECTS LSB FIRST
FIRST BIT
RECEIVED
TIME-SLOT DATA
LSB
BIT 0
MSB
BIT 7
MSB
BIT 7
LSB
BIT 0
DIRECTION OF RECEPTION
RLBIT = 1 (RECEIVE LSB FIRST)
a b c d e f g h
HDLC
A B C D E F G H
H G F E D C B A
TRANSMIT FIFO
TRANSMITTER HDLC
PROCESSES LSB FIRST
FIRST BIT
TRANSMITTED
TIME-SLOT DATA
MSB
BIT 7
LSB
BIT 0
MSB
BIT 7
LSB
BIT 0
DIRECTION OF TRANSMISSION
TLBIT = 0 (TRANSMIT MSB FIRST)
a b c d e f g h
HDLC
A B C D E F G H
H G F E D C B A
RECEIVE FIFO
RECEIVER HDLC
EXPECTS LSB FIRST
FIRST BIT
RECEIVED
TIME-SLOT DATA
LSB
BIT 0
MSB
BIT 7
MSB
BIT 7
LSB
BIT 0
DIRECTION OF RECEPTION
RLBIT = 0 (RECEIVE MSB FIRST)
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