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參數(shù)資料
| 型號： | T7121 |
| 廠商： | Lineage Power |
| 英文描述： | HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口) |
| 中文描述： | 為ISDN接口的HDLC（高保真- 64）（應(yīng)用于綜合業(yè)務(wù)數(shù)字網(wǎng)的的HDLC（高階數(shù)據(jù)鏈路）接口） |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 685K |
| 代理商： | T7121 |
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16
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Bit Masking
When in the TDM highway mode (HWYEN, R0—B7 = 1), the HIFI-64 can be programmed to mask any combina-
tion of bits in a byte. As an example, this feature is used to process 16 kbits/s D-channel data where only 2 bits in
each byte are looked at when receiving, and where only 2 bits are transmitted during an 8-bit time slot. Using this
option, the HIFI-64 is able to support effective intermediate data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s.
The receiver ignores bit positions that are masked (cleared to 0) in the receiver bit mask register (R12). The trans-
mitter outputs high impedance (3-state) during the bit times specified (cleared to 0) in the transmitter bit mask reg-
ister (R13). The user can program any combination of bits to be masked in the receiver and transmitter
independently.
Upon chip reset, the default is as follows:
1. The receiver defaults to recognize all incoming data as valid (i.e., no masking).
2. The transmitter defaults to a state where all bits are masked.
The user must unmask the bits to be transmitted. This eliminates the problem of the HIFI-64 transmitting before the
time slot has been programmed in registers 7, 9, and 10.
Figures 8 and 9 show how 16 kbits/s operation is achieved by using the bit-masking option.
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