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參數(shù)資料
| 型號： | T7121 |
| 廠商： | Lineage Power |
| 英文描述： | HDLC Interface for ISDN (HIFI-64)(應用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口) |
| 中文描述： | 為ISDN接口的HDLC（高保真- 64）（應用于綜合業(yè)務數(shù)字網(wǎng)的的HDLC（高階數(shù)據(jù)鏈路）接口） |
| 文件頁數(shù)： | 8/68頁 |
| 文件大?。?/td> | 685K |
| 代理商： | T7121 |
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8
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Microprocessor Bus Interface
Addressing
The T7121 is designed to easily interface with 8-bit
microprocessors. The microprocessor bus interface
allows parallel asynchronous access to a bank of 19
registers (R0—R15 and AR11—AR13). The bus inter-
face is compatible with most microprocessors. The reg-
isters occupy 16 continuous locations in the memory
map of a controlling microprocessor, and the registers
are accessed under the control of the following signals:
address select (A0—A3 or AD0—AD7), address latch
enable (ALE), chip select (
CS
(
WR
). When multiplexed address and data lines are
used, the ALE signal is used to latch the address
present on AD0—AD3 and AD6. AD6 has a special
use in the block-move mode. See the Block Move sec-
tion under the FIFO Memory Buffers section. ALE
should be tied high when separate address and data
are used.
), read (
RD
), and write
Registers 11, 12, and 13 have alternate meanings
depending on the value of the Alternate (ALT) bit in the
chip configuration register (R0—B4). The alternate reg-
isters are accessed by setting the ALT bit (R0—B4) to
1. All subsequent addressing of registers 11 through 13
then refers to the alternate registers (AR11—AR13).
Returning to the foreground register set is accom-
plished by clearing the ALT bit (R0—B4) to 0.
Interrupts
A programmable interrupt output, INT, is provided to
alert the microprocessor when the device needs ser-
vice. Associated with the interrupt system are the IPOL
bit in register 0 (R0—B1), the interrupt mask register
(R14), and the interrupt status register (R15). The
polarity of the INT signal (pin 14) is programmable by
setting the IPOL bit in register 0 (R0—B1). The inter-
rupt mask register can be programmed so that only
certain conditions cause the INT signal to be asserted.
The interrupt status register (R15) reveals the source of
the interrupt.
Register 14, the interrupt mask register, controls the
operation of the INT pin. Masking an interrupt means
that no transition of the INT pin is generated for any
occurrence of that interrupt condition. The INT signal is
enabled upon the first occurrence of any unmasked
interrupt condition. The INT signal remains until the
interrupt is acknowledged by reading the interrupt sta-
tus register (R15). Unmasked interrupts occurring
between the first unmasked interrupt and the status
register read do not cause a transition of the INT pin. If
a second interrupt occurs during a read of the interrupt
status register (R15), the INT signal is disabled after
the read and then reasserts itself. This deassertion can
actually be much less than one cycle, and no minimum
width is guaranteed. One method to ensure that the
second interrupt is detected is to use an edge-sensed
INT pin on the processor. If this is not available, the
interrupt service routine should reread the interrupt sta-
tus register to determine if an interrupt occurred during
the clearing of the first interrupt.
Masking all interrupts effectively disables the INT pin. It
is possible to mask a currently active interrupt. Doing
so causes a transition of the INT pin from active to
inactive if the masked interrupt was the only active
interrupt. Likewise, unmasking an interrupt that is cur-
rently asserted causes an INT pin transition from inac-
tive to active if all other unmasked interrupts were
currently inactive. Interruptable conditions are always
reported in register 15, even if the interrupt pin transi-
tion is masked. Thus, polled interrupt systems are also
supported. Note that a transition of the INT pin occurs
only if the interrupting condition is unmasked and no
other unmasked, unacknowledged interrupt exists.
The HIFI-64 allows two modes of interrupt: dynamic
and nondynamic. The mode is controlled by setting the
DINT (Dynamic INTerrupt) bit in register 0 (R0—B0). If
DINT (R0—B0) is 0 (nondynamic mode), the interrupt
bits in the interrupt status register (R15) are cleared
directly by a read of register 15. The condition causing
the interrupt must go away and come back in order to
reassert the interrupt. If DINT (R0—B0) is set to 1
(dynamic mode), the transmitter empty (R15—B1) and
receiver full (R15—B3) interrupts are cleared only
when the condition causing the interrupt has been rem-
edied (all other interrupts are cleared by reading the
interrupt status register [R15]). In addition, the INT sig-
nal (pin 14) remains enabled until the condition(s)
causing the interrupt has been remedied.
A dynamic version of the transmitter empty interrupt,
transmitter empty dynamic (TED), is provided in the
transmitter status register (R2—B7). TED behaves
dynamically regardless of the value of the DINT bit
(R0—B0). TED does not cause a transition of the INT
pin.
In transparent mode, the REOF, RIDL, and UNDABT
interrupts are disabled. TDONE is used to indicate a
transmitter underrun and can be used to determine
transmission end. Additionally, the MSTAT bit
(AR11—B3) can be used as a polled interrupt to deter-
mine the beginning of receive data. A transition of the
INT pin can be programmed for the beginning of
receive data by setting the initial receiver-full interrupt
level RIL (R5—B[5—0]) to 1 byte.
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