參數(shù)資料
型號(hào)： T7121
廠商： Lineage Power
英文描述： HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口)
中文描述： 為ISDN接口的HDLC（高保真- 64）（應(yīng)用于綜合業(yè)務(wù)數(shù)字網(wǎng)的的HDLC（高階數(shù)據(jù)鏈路）接口）
文件頁(yè)數(shù)： 63/68頁(yè)
文件大?。?/td> 685K
代理商： T7121
Lucent Technologies Inc.
63
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Appendix
This Appendix is intended to answer questions that
may arise when using the T7121 HDLC Interface for
ISDN. These questions have been compiled from cus-
tomer inquiries.
The questions and answers are divided into four
operational categories: transparent mode, HDLC
mode, general features, and power and ground.
Transparent Mode
Q1
:
Since there is no interrupt due to a MATCH, how
can a MATCH be detected as soon as one
occurs
A1
:
Initially, the receive threshold should be set to 1.
An interrupt will then occur on the first data byte
after the MATCH. Next, the MATCH status should
be read and a determination made as to whether
the application requires a threshold other than 1;
if it does, the threshold should be changed
accordingly.
Q2
:
In transparent mode, the transmit idle character
(TIC0—TIC7, AR13) and the receiver match
character (RMC0—RMC7, AR12) are set to the
same value and local loopback is enabled
(LLOOP, R6, b1 = 1). After enabling the transmit-
ter and receiver, the interrupt for receiver over-
runs occurs, and the receive FIFO is full of match
characters (as expected). The end-of-frame bit
(EOF, R4, b7) is also set. Is this normal
A2
:
Yes, this is normal operation. Although end-of-
frame has no meaning in transparent mode, the
EOF bit acts as another indication that the
receiver has been overrun.
Q3
:
In the transparent mode, what does a TDONE
(R15, bit 0) of 1 mean
A3
:
It means the transmit FIFO is empty. If the FIFO
is empty in the transparent mode configuration, a
TDONE interrupt will immediately occur, along
with a TE interrupt, even before enabling the
transmitter.
HDLC Mode
Q4
:
If the transmit FIFO is loaded and then enabled,
information is sometimes lost (in the HDLC
mode), is there an explanation for this
A4
:
As soon as the FIFO is loaded, the data is
prepared for HDLC transmission. If the micropro-
cessor (which is asynchronous with the highway)
turns on the transmitter at the wrong time relative
to the frame sync, then the first byte is missed.
The first byte is the open flag, so the first frame of
HDLC data is lost.
There are two solutions. The first one is to enable
the transmitter and then load the FIFO. As long
as the FIFO is loaded faster than data can be
sent out, the system will operate without any
abort interrupts.
The second solution is to set the idle character to
look like an open flag, then load the FIFO, and
then enable the transmitter; this means there is
always going to be an open flag. If the idle char-
acter is then changed to all 1s before the FIFO is
empty, all subsequent frames will have the open
flag, as expected, and all 1s will be sent as idle.
Q5
:
When using the first solution described for Q4,
1-byte frames cannot always be sent; why
A5
:
One-byte frames may not be sent properly
because data may be sent before the close infor-
mation register can be written—if the transmitter
is enabled when the FIFO is written, data may be
sent as soon as the FIFO is written—resulting in
a transmit abort. However, in a real HDLC
environment, address information plus data usu-
ally prevents the problem from occurring.
Q6
:
Can the T7121 recognize the shared flag
between consecutive frames In other words,
can the closing flag of the first frame be the open-
ing flag of the second frame, i.e., Flag Data1
CRC CRC Flag Data2 . . . .
A6
:
Yes, this is considered normal operation.
Q7
:
Regarding the EOF status byte, when the bad
byte count bit (bit 4) is activated (high), does the
bad CRC bit (bit 7) also activate
A7
:
CRC bits are checked on a bit-per-bit basis.
Therefore, it is possible, but very unlikely, that a
bad byte count could occur without a bad CRC
indication.
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