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參數(shù)資料
| 型號： | T7121 |
| 廠商： | Lineage Power |
| 英文描述： | HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口) |
| 中文描述： | 為ISDN接口的HDLC（高保真- 64）（應(yīng)用于綜合業(yè)務(wù)數(shù)字網(wǎng)的的HDLC（高階數(shù)據(jù)鏈路）接口） |
| 文件頁數(shù)： | 27/68頁 |
| 文件大?。?/td> | 685K |
| 代理商： | T7121 |
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Lucent Technologies Inc.
27
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
In the remote loopback mode:
CLKR must equal or be synchronous with CLKX. We recommend clocking both transmit and receive data with
CLKX (R5—B6 set to 1).
I
Receive and transmit bit masks (R12 and R13) should be programmed to the same value.
I
Transmitted data is retimed. If HWYEN = 0 (R0—B7), the transmitted data is retimed with a maximum delay of
2 bits. If HWYEN = 1 (R0—B7), the received data is transmitted in the first programmed time slot after the
receive time slot is complete.
I
Received data is retransmitted on the DXA and/or the DXB output, depending on DXAC and DXBC.
I
The transmitter should be disabled. The receiver can be disabled or, if desired, enabled. Received data is sent
as usual to the receive FIFO if the receiver is enabled.
5-5037
Figure 11. Remote Loopback Mode
CAUTION: Do not use local and remote loopback modes at the same time. Such use results in an
unknown state in the chip which only a full reset of the chip can clear.
HDLC
CHI
TRANSMITTER
DXA
DXB
(USER-SELECTED)
FIFO
HDLC
CHI
FIFO
RECEIVER
DRA
OR
DRB
(USER-SELECTED)
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