參數(shù)資料
型號(hào)： T7121
廠商： Lineage Power
英文描述： HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口)
中文描述： 為ISDN接口的HDLC（高保真- 64）（應(yīng)用于綜合業(yè)務(wù)數(shù)字網(wǎng)的的HDLC（高階數(shù)據(jù)鏈路）接口）
文件頁(yè)數(shù)： 9/68頁(yè)
文件大?。?/td> 685K
代理商： T7121
Lucent Technologies Inc.
9
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Resets
The T7121 is fully reset by either asserting the RESET
pin (hardware reset) or by asserting both the TRES
(R6—B5) and RRES (R6—B4) bits simultaneously
when writing to register 6 (software reset). A full reset
results in all registers returning to their default condi-
tions and all logic returning to a known state. No clock
input is necessary. During a hardware reset, all outputs
are 3-stated. Thus, the RESET pin can be used for
bed-of-nails testing. During a software reset, outputs
are not automatically 3-stated. Output pin states are
determined by their default register configuration. Both
transmit data pins (DXA and DXB) 3-state since the
default register configuration is both transmit pins dis-
abled. The INT pin is high.
In addition, the transmitter and receiver can be individ-
ually reset. When TRES (R6—B5) is high and RRES
(R6—B4) is low during a write of register 6, the trans-
mitter is independently reset. The transmitter FIFO
pointers return to default values, resulting in the loss of
any untransmitted data, and the transmitter state
machine is returned to the idle state. Transmitter inter-
rupts are cleared, except for the TE (R15—B1) inter-
rupt, which is asserted and causes a transition on the
INT pin if unmasked (TEIE, R14—B1 = 1). Only trans-
mit status registers and interrupts change to reflect the
reset. Disabling the transmitter does not cause an
automatic reset. When the transmitter has been active
and then subsequently disabled, a TRES is needed to
restore it to a known state.
When TRES (R6—B5) is low and RRES (R6—B4) is
high during a write of register 6, the receiver is inde-
pendently reset. A receiver reset causes the receiver
FIFO pointers to return to their default values, resulting
in the loss of unread data in the FIFO. The receiver is
returned to a known state, and all currently asserted
receiver interrupts are cleared. The receiver should be
reset whenever it was active and subsequently dis-
abled to ensure correct operation. Only receiver status
and interrupt bits are affected in the register set. Dis-
abling the receiver does not cause a receiver reset.
FIFO Memory Buffers
The HIFI-64 is equipped with a transmit FIFO and a
receive FIFO, each with a capacity of 64 bytes.
Transmit FIFO
Data to be transmitted is loaded via the data register
(R3) into the 64-byte transmit FIFO. Multiple frames
can be placed in the FIFO. In HDLC mode, the final
byte of each frame is marked by writing the transmit
frame complete bit TFC (R1—B7). The transmitter can
also be instructed to abort a frame by using the trans-
mit abort bit TABT (R1—B6) (HDLC mode only). Trans-
mission status is available in the transmit status
register and via the transmit interrupts. The transmitter
status register (R2) indicates how many additional
bytes can be added to the FIFO. The transmitter inter-
rupt trigger level (TIL) can be programmed in the trans-
mitter control register (R1—B[5—0]) to tailor service
time intervals to the system environment. The transmit-
ter empty (TE) interrupt bit is set in the interrupt status
register (R15—B1) when the FIFO has sufficient empty
space to add the number of bytes specified in the TIL. If
the TE interrupt mask TEIE (R14—B1) is 1, the occur-
rence of a TE interrupt condition causes a transition of
the interrupt pin if no other unmasked interrupts are
currently active. In dynamic interrupt mode (DINT,
R0—B0 = 1), this interrupt remains set until the condi-
tion is cleared. In nondynamic interrupt mode
(DINT, R0—B0 = 0), this interrupt is cleared by reading
R15. A TDONE (R15—B0) interrupt occurs for each
HDLC frame completed. In the transparent mode, a
TDONE interrupt occurs when the transmit FIFO emp-
ties. In HDLC mode, an UNDABT (R15—B2) interrupt
is issued if the transmitter underruns.
There is no interrupt indication of a transmitter overrun
that is writing more data than empty spaces exist.
Overrunning the transmitter causes the last valid data
byte written to be repeatedly overwritten, resulting in
missing data in the frame.
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