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參數(shù)資料
| 型號(hào)： | T7121 |
| 廠商： | Lineage Power |
| 英文描述： | HDLC Interface for ISDN (HIFI-64)(應(yīng)用于ISDN的HDLC（高階數(shù)據(jù)鏈路）接口) |
| 中文描述： | 為ISDN接口的HDLC（高保真- 64）（應(yīng)用于綜合業(yè)務(wù)數(shù)字網(wǎng)的的HDLC（高階數(shù)據(jù)鏈路）接口） |
| 文件頁(yè)數(shù)： | 34/68頁(yè) |
| 文件大?。?/td> | 685K |
| 代理商： | T7121 |
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34
Lucent Technologies Inc.
Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
(continued)
Table 12. Register R5—Receiver Control Register
R5—B7
P17CTL
(0)
R5—B6
P21CTL
(0)
R5—B5
RIL5
(0)
R5—B4
RIL4
(0)
R5—B3
RIL3
(0)
R5—B2
RIL2
(0)
R5—B1
RIL1
(0)
R5—B0
RIL0
(0)
Register
R5
Bit
Symbol
RIL0—RIL5
Name/Function
B(0—5)
Receiver Interrupt Level.
These bits determine when a receiver
full (RF) interrupt is triggered. The value programmed in RIL equals
the number of bytes in the receive FIFO which triggers an RF inter-
rupt. For example, a code of 001111 means an interrupt is gener-
ated when the receive FIFO contains 15 or more bytes. The code
000000 is a special case and means an interrupt is generated only
when the receive FIFO is actually full.
Pin 21 Control.
This bit controls the functionality of pin 21. When
this bit is set to 1, pin 21 is configured as DRB, and received data is
clocked by CLKX. When this bit is cleared to 0, pin 21 is configured
as CLKR and provides the timing for received data.
Pin 17 Control.
This bit controls the functionality of pin 17. When
this bit is cleared to 0, pin 17 is configured as DXB output. In this
configuration, data is transmitted on DXB. When this bit is set to 1,
pin 17 is configured as
TCSA
. This overrides the setting of DXBC
(R7—B6). In this configuration, data can only be transmitted on
TDM highway A through the DXA pin (pin 19). If HWYEN (R0—B7)
is 0,
TCSA
is continuously low.
R5
B6
P21CTL
R5
B7
P17CTL
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