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| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機(jī)）微處理器（64位精簡指令集系統(tǒng)計算機(jī)微處理器） |
| 文件頁數(shù)： | 11/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
11
5. TX4955/TX4956 System Interface
5.1
TX4955 and TX4956
System interface protocols for the TX4955 and TX4956 are fundamentally the same. This document
provides explanations based on the TX4956.
TX4955: 32-bit bus interface
TX4956: Has two modes: 64-bit bus interface mode and 32-bit bus interface mode
5.2
Terminology
The following terms are used in this section.
External agent: Logic device that is directly connected to the processor via the system interface
so a processor can issue (instructions).
System event: Event issued inside a processor which, when generated, means that access to
external system resources is required.
Sequence: Strict order of requests that the processor generates in order to provide service for
system events.
Protocol: Shift of signals for each cycle generated on the system interface so processor requests
or external requests can be asserted.
Syntax: Strict definition of the bit pattern on the encoded bus (command bus, etc.).
5.3
Explanation of System Interface
The TX4956 processor supports 64-bit address/data interfaces. This processor makes it possible to
construct a processor system by processors and main memory. This processor also supports 32-bit
external address/data interfaces. System interfaces consist of the following components:
64-bit address/data bus, SysAD
8-bit SysAD check bus, SysADC
9-bit command bus, SysCmd
1-bit SysCmd check parity, SysCmdP
handshake signals
– RdRdy*, WrRdy*
– ExtRqst*, Release*
– ValidIn*, ValidOut*
The TX4956 processor accesses external resources using the system interface in order to correct cache
misses, uncached operation, and other problems.
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