參數(shù)資料
型號(hào)： TMPR4956F
廠商： Toshiba Corporation
英文描述： 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 9/60頁(yè)
文件大?。?/td> 244K
代理商： TMPR4956F
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
9
4.3.4 JTAG INTERFACE
PIN NAME
I / O
FUNCTION
JTDI
I
JTAG data input / Debug interrupt input
Run-time mode : input serial data to data/instruction register of JTAG.
Real-time mode : interrupt line to change the debug unit state from real time
mode to Run-time mode.
JTAG clock input
The processor receives a serial clock on JTCK. On the rising edge of JTCK,
both JTDI and JTMS are sampled.
JTAG data output / PC Trace output
Run-time mode : output serial data from data/instruction register of JTAG.
Real-time mode : output non-sequential program.
JTAG command
JTAG command signal, indicating the incoming serial data is command data.
Debug Clock
A clock output for a real-time debug system. The timing of a serial monitor bus
and PC trace interface signal are all defined by this debug clock DCLK. The
operation clock of the TX4956 is divided by 3 at the time of a serial monitor bus
operation.
PC trace status
Output PC trace status information and the mode of the serial monitor bus.
PC trace output
Output a non-sequential program counter at DCLK.
Test Reset input
A reset input for a real-time debug system. When TRST* is asserted, the debug
support unit (DSU) is initialized.
JTCK
I
JTDO/TPC(0)
O
JTMS
I
DCLK
O
PCST(8:0)
O
TPC(3:1)
O
TRST*
I
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