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參數(shù)資料
| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 25/60頁 |
| 文件大小： | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
25
5.6.4 Uncached load or store
When performing uncached load operations, the processor issues non-coherent read requests for double
words, partial double words, words, or partial words. Also, when performing uncached store operations,
the processor issues write requests for double words, partial double words, words, or partial words.
When in the 64-bit mode, the TX4956 judges that there is valid parity and data in the entire 64-bit SysAD
bus even for data requests of less than double words. Even if there was a partial word request for
example, all parity must be correctly returned for all 64 bits. If not, then parity check must be disabled.
When in the 32-bit mode, the TX4956 judges that there is valid parity and data in the entire 32-bit SysAD
bus even for data requests of less than words. Even if there was a partial word request for example, all
parity must be correctly returned for all 32 bits. If not, then parity check must be disabled.
All write transactions by the TX4956 are buffered in the 4-stage write buffer of the system interface. If
there are entries in the write buffer when a block request is required, the write buffer is flushed before a
read request is generated (for cache misses or read transactions to uncached areas). Data cache misses or
uncached data load transactions flush the write buffer.
5.6.5 Cache instruction operation
Various operations are made available to the Cache instruction in order to maintain the primary cache
status and contents. When Cache instruction operations are in progress, write requests or invalidate
requests can be issued from the processor.
5.6.6 Load Linked Store Conditional Operation
TX4956 and TX4955 are not supporting the Load-Link/Store-Conditional instruction sequence.
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