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參數(shù)資料
| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計(jì)算機(jī)）微處理器（64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 30/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
30
Figure 7-4 Reissue Write Protocol
3.
Pipeline write
Similar to when in the R4000 compatible write mode, the pipeline write protocol issues a write
operation if the WrRdy* signal is asserted for 1 cycle 2 cycles before the write operation is issued.
However, the 2 cycles of dummy data after the write operation are deleted. The external agent must
be able to accept one write operation or more after WrRdy* is deasserted. Figure 7-5 illustrates this
protocol.
Third, fourth cycle Addr0/Data0 is issued by asserting (Low) the WrRdy* signal in the first cycle.
Fifth, sixth cycle Addr1/Data1 is issued by asserting (Low) the WrRdy* signal in the third cycle.
Addr2 is not issued in the seventh cycle when the WrRdy* signal is deasserted (High) in the fifth
cycle. Addr2/Data2 is issued in the tenth, eleventh cycle by asserting the WrRdy* signal again in
the eighth cycle.
Master
Clock
Cycle
SysAD bus
SysCmd bus
WrRdy*
1
2
3
4
6
10
11
12
Write
Write
Write
NEOD
NEOD
NEOD
Addr0
Addr1
Addr1
Data0
Data1
Data1
Issue
No
is5
No
is7
No
is8
No
is9
Issue
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