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參數(shù)資料
| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機(jī)）微處理器（64位精簡指令集系統(tǒng)計算機(jī)微處理器） |
| 文件頁數(shù)： | 31/60頁 |
| 文件大小： | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
31
Figure 7-5 Pipeline Write Protocol
5.7.5
Processor block write request
The master state system interface is used to issue processor block write requests. The protocol is the same
for both the 64-bit bus mode and the 32-bit bus mode. Figure 7-6 illustrates a processor non-coherent
block request made for 8-word data with the “D” data pattern when in the 64-bit bus mode.
Because TX4956 is a thing of 64-bit bus width, 8-word data get off with four data transmission.
1.
Processor sends a write command to the SysCmd bus, then sends a write address to the SysAD bus.
2.
Processor asserts the ValidOut* signal.
3.
Processor sends data identifier to the SysCmd bus and sends data to the SysAD bus.
4.
Processor asserts the ValidOut* signal only for the number of cycles required to transfer the data
block.
5.
Final data cycle directive must be included in data identifiers for the final data cycle.
Note : There is transmission protocol of Processor block write request three kinds same as Processor single
write requests. With later G2SConfig-Regster, these modes are selected.
Master
Clock
Cycle
SysAD bus
SysCmd bus
WrRdy*
1
2
3
4
5
6
7
10
11
12
Write
Write
Write
NEOD
NEOD
NEOD
Addr0
Addr1
Addr2
Data0
Data1
Data2
Issue
Issue
No
issue
No
is8
No
is9
Issue
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