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| 型號(hào)： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計(jì)算機(jī)）微處理器（64位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
17
5.5
Processor Requests and External Requests
Requests are broadly categorized as processor requests and external requests. This section will describe
these two categories.
When a system event is generated, either a single request or a series of requests (referred to as processor
requests) are issued via the system interface so the processor can access an external resource and invoke
the service for the event. In order for this operation to be performed properly, the processor system
interface must be connected to a system agent that meets the two following conditions:
1)
It is in compliance to the system interface protocol.
2)
It can regulate access to system resources.
An external agent that requests access to the processor cache or the status registers generates an external
request. This access request is transferred via the system interface. Figure 5-1 illustrates the system event
and request cycles.
Figure 5-1 Requests and System Events
5.5.1
Rules relating to processor requests
The following rules apply to processor requests.
After a processor read request is issued, the processor cannot issue the next read request until after
it receives a read response.
When in the R4000 compatible mode, after a write request is issued, at least 4 cycles must pass
from when the write request issue cycle is complete until the processor can issue the next request.
This is because two dummy system cycles are inserted as illustrated in Figure 5-2 by consecutive
write requests of single data cycles.
Processor Request
Read
Write
Processor Request
Read
Write
Null
TX4956
System Events
Load miss
Store miss
Store bit
Uncached load/store
Cache operation
External agent
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