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| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機(jī)）微處理器（64位精簡指令集系統(tǒng)計算機(jī)微處理器） |
| 文件頁數(shù)： | 40/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
40
5.8.2 Independent transfer on SysAD bus
A majority of applications connect the processor and external agent interior (both directions), and register
format transceivers together in a point-to-point manner via the SysAD bus. The only two SysAD bus
drives available for such applications are the processor and the external agent.
Depending on the application, it may be necessary to make additional connections on the SysAD bus for
drivers and receivers to transfer data using the SysAD bus without involving the processor. Such transfers
are referred to as independent transfers. In order to perform independent transfers, the external agent must
use arbitration handshake signals and external null requests to properly tune SysAD bus control.
Independent transfer is performed on the SysAD bus according to the following steps.
1.
The external agent requests access to the SysAD bus in order to issue an external request.
2.
The processor releases the system interface and puts it in the slave state.
3.
The external agent can independently transfer data using the SysAD bus. However, the ValidIn*
signal must be asserted during that transfer.
4.
When transfer is complete, the external agent must issue a system interface release null request and
return the system interface to the master state.
5.9 System Interface Command and Data Identifier
In the case of a processor, there is a response time for each kind of processor transaction and for each
external request. A minimum and maximum cycle count has been prescribed for each response time.
Since processor requests themselves are restrained by system interface request protocols, checking the
protocols makes it possible to determine the cycle count required for requests. The interval for the next
interface operation is variable within the range of the minimum and maximum cycle counts.
Stand-by time from when an external request is received and the processor releases the system
interface, until when the interface enters the slave state (release latency).
Response time to external request that requires a response (external response latency).
5.9.1 Release latency
Broadly defined, release latency is the number of cycles for which it is possible to wait from when the
processor receives an external request until when the system interface is released and shifts to the slave
state. If there are no processor requests currently in progress, the processor must delay release of the
system interface for a few cycles since it is internal operation. Therefore, if release latency is strictly
defined, it becomes the cycle count from when the ExtRqst* signal is asserted until when the Release*
signal is asserted.
There are three types of release latency.
Category 1: If external request signal is asserted 2 cycles before the final cycle of the processor
request
Category 2: If external request signal is asserted during processor request or is the final cycle even
if it is asserted
Category 3: If processor automatically shifts to the slave state
Table 9-1 indicates the minimum and maximum release latency inherent to categories 1, 2, and 3.
However, note that these cycle counts may be changed at any time.
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