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參數(shù)資料
| 型號： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 64位RISC（精簡指令集計算機）微處理器（64位精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 18/60頁 |
| 文件大小： | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
18
Figure 5-2 Timing of Consecutive Write Cycles
5.5.2
Processor requests
The term “processor request” refers to either a single request or a series of requests issued via the system
interface in order to access external resources. As illustrated in Figure 5-3, there are two types of
processor request: read and write.
Figure 5-3 Processor Requests
Read requests are requests that read data from main memory or other memory resources in block double
word, partial double word, word, and partial word units.
Write requests are requests that write data to main memory or other system resources in block, double
word, partial double word, word, and partial word units.
Processor requests are managed by the TX4956 processor in the same manner as the R4000/R4400 non-
secondary cache mode.
The processor issues requests strictly according to a sequential method. In other words, the processor
cannot issue the next request while a previous request is on hold. For example, after issuing a read
request, the processor waits for a read response before issuing the next request. The processor only issues
Processor request
Read
Write
TX4956
External agent
1
2
4
5
6
7
8
9
10
3
Write #1
Write #2
Cycle
1
2
3
4
Cycle
Master Clock
SysAD Bus
WdRdy*
ValidOut*
Addr
Data
Addr
Data
Dummy
Dummy
Dummy
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