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參數(shù)資料
| 型號(hào)： | TMPR4956F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4956F |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
35
data when it receives an external read request.
5.7.9 External null request protocol
The processor only supports one external null request. The system interface release external null request
returns the system interface from the slave state to the master state. This request does not affect any other
processors.
The only processing the external null request does is to have the processor return the system interface to
the master state.
Figure 7-9 illustrates the timing of the external null request, which consists of the following steps.
1.
The external agent requests use of the system interface by asserting ExtRqst*.
2.
The processor asserts Release*, then the system interface is released from the processor and goes into
the slave state.
3.
The external agent drives the system interface, sends the external null request command to the
SysCmd bus, then asserts the ValidIn* signal for 1 cycle.
4.
The SysAD bus is not available during the external null request address cycle (there are no valid data
in the bus).
5.
The null request ends when the address cycle is issued.
In the case of a system interface release null request, the external agent releases the SysCmd bus and
SysAD bus so the system interface can return to the master state. This protocol is the same for both the
32-bit and 64-bit bus modes.
Figure 7-9 System Interface Release External Null Request
Master
Clock
SysAD bus
Cycle
SysCmd bus
ValidOut*
ValidIn*
ExtRqst*
Release*
1
2
3
4
5
6
7
8
9
10
11
12
Unsd
4
SINull
5
3
Slave
Master
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