參數(shù)資料
型號(hào)： TMPR4956F
廠商： Toshiba Corporation
英文描述： 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器)
中文描述： 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器）
文件頁(yè)數(shù)： 34/60頁(yè)
文件大?。?/td> 244K
代理商： TMPR4956F
TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
34
5.7.8 External read request protocol
External read requests are requests that read 1 word of data from processor-internal resources such as
registers. External read requests cannot be partitioned. Namely, it is not possible to generate other
requests between an external read request and the corresponding read response.
Figure 7-8 illustrates the timing of external read requests, which consist of the following steps.
1.
The external agent requests use of the system interface by asserting ExtRqst*.
2.
The processor asserts Release* for 1 cycle, then releases the system interface by deasserting Release*
and puts the interface into the slave state.
3.
After Release* is deasserted, the SysAD bus and SysCmd bus are set to tri-state for 1 cycle.
4.
The external agent sends a read request command to the SysCmd bus, sends a read request address to
the SysAD bus, and asserts ValidIn* for 1 cycle.
5.
After sending the above address and command, the external agent sets the SysCmd and SysAD busses
to tri-state, makes it possible for the processor to drive them, then releases them both. The processor
that accessed the data to be read returns the data to the external agent. Therefore, the processor sends
the data identifier to the SysCmd bus, sends the response data to the SysAD bus, then asserts
ValidOut* for 1 cycle. This data identifier indicates that data are the response data of the final data
cycle.
6.
The system interface is in the master state. The processor continues to drive the SysCmd bus and
SysAD bus even after the read response is returned.
Note:
Timing of the SysADC bus and SysCmdP bus is the same as that for the SysAD and SysCmd
busses, respectively.
External read requests can read data from only a single word in the processor. If data elements other than
a word are requested, the processor response is not defined.
Figure 7-8 External Read Request when System Interface is in the Master State
Note:
The processor contains no resources that can read by way of external read requests. The
processor returns data identifiers with SysCmd(5) of the error data bits set along with undefined
Master
Clock
SysAD bus
Cycle
SysCmd bus
ValidOut*
ValidIn*
ExtRqst*
Release*
1
2
3
4
5
6
7
8
9
10
11
12
Master
Slave
Master
1
Addr
Read
Data0
NEOD
2
3
4
5
6
6
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