- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365965 > TS8882VF20 PDF資料下載
參數(shù)資料
| 型號： | TS8882VF20 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 1703K |
| 代理商： | TS8882VF20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
12
TS68882
2119A
–
12/01
Notes:
1. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise
noted. The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will
be linear between 0.8 volts and 2.0 volts.
2. These specifications only apply if the TS 68882 has completed all internal operations initiated by the termination of the pre-
vious bus cycle when DS was negated.
3. Synchronous read cycles occur only when the save or response CIR locations are read.
4. This specification only applies to systems in which back-to-back accesses (read-write or write-write) of the operand CIR can
occur. When the TS 68882 is used as a coprocessor to the TS 68020/68030, this can occur when the addressing mode is
immediate.
5. If the SIZE pin is not strapped to either V
CC
or GND, it must have the same setup times as do addresses.
6. If the SIZE pin is not strapped to either V
CC
or GND, it must have the same hold times as do addresses.
7. This number is reduced to 5 nanoseconds if DSACK0 and DSACK1 have equal loads.
8. START is not an external signal; rather, it is the logical condition that indicates the start of an access. The logical equation
for this condition is START = CS + AS + (R/W
·
DS).
9. If a subsequent access is not a FPCP access, CS must be negated before the assertion of AS and/or DS on the non-FPCP
access. These specifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transi-
tions in CS must not occur simultaneously with transitions of AS or DS. This is not a requirement of the TS 68882).
Test Conditions
Specific to the
Device
Test Load
The applicable loading network shall be as defined in column
“
Test conditions
”
of Table 2,
referring to the loading network number as shown in Figure 5.
22
START false to DSACK0 and DSACK1
high impedance
(8)
70
55
55
40
ns
23
START true to clock high (synchronous
read)
(3)(8)
0
0
0
0
ns
24
Clock low to data-out valid synchronous
read)
(3)
105
80
60
45
ns
25
START true to data-out valid (synchronous
read)
(3)(8)
0
1.5
105+
2.5
1.5
80 +
2.5
1.5
60+
2.5
1.5
45-
2.5
ns
Clks
26
Clock low to DSACK0 and DSACK1
asserted (synchronous read
(3)
75
55
45
30
ns
27
START true to DSACK0 and DSACK1
asserted (synchronous read)
(3)(8)
1.5
75+
2.5
1.5
55+
2.5
1.5
45+
2.5
1.5
30-
2.5
ns
Clks
Table 7.
AC Electrical Characteristics - Read and Write Cycles
V
CC
= 5.0 V
dc
± 10%; GND = 0 V
dc;
Tc = -55
°
C/+125
°
C or Tc = -40
°
C/+85
°
C (see Figure 7, Figure 8, Figure 9)
N°
Parameter
16.67 MHz
20 MHz
25 MHz
33.33 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS88915T | TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| TS902AID | Voltage-Feedback Operational Amplifier |
| TS902AIN | Voltage-Feedback Operational Amplifier |
| TS902BID | Voltage-Feedback Operational Amplifier |
| TS902BIN | Voltage-Feedback Operational Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS88915T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| TS88915TMR70 | 功能描述:IC CLK DVR 8OUT PLL 70MHZ 29PGA RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| TS88915TMW70 | 功能描述:IC CLK DVR 8OUT PLL 70MHZ 28LCCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| TS88915TMWB/T55 | 制造商:e2v technologies 功能描述: |
| TS88915TMWB/T70 | 制造商:e2v technologies 功能描述:PLL Clock Driver Single 35MHz to 70MHz 28-Pin LDCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。