參數(shù)資料
型號： TS8882VF20
文件頁數(shù)： 28/42頁
文件大?。?/td> 1703K
代理商： TS8882VF20
28
TS68882
2119A
–
12/01
Branch, Set, and
Trap-on Condition
The floating-point branch, set, and trap-on condition instructions implemented by the TS
68882 are similar to the equivalent integer instructions of the TS 68000 Family processors,
except that more conditions exist due to the special values in IEEE floating-point arithmetic.
When a conditional instruction is executed, the TS 68882 performs the necessary condition
checking and tells the MPU whether the condition is true or false; the MPU then takes the
appropriate action. Since the TS 68882 and TS 68020/TS 68030 are closely coupled, the float-
ing-point branch operations executed by the pair are very fast.
The TS 68882 conditional operations are:
where:
cc is one of the 32 floating-point conditional test specifiers as shown in Table 9.
rs
FBcc
Branch
FDBcc
Decrement and Branch
FScc
Set Byte According to Condition
FTRAPcc
Trap-on Condition (with an Optional
Parameter)
Table 9.
Floating-point Conditional Test Specifiers
Mnemonic
Definition
Note: The following conditional tests do not set the BSUN bit in the status register exception byte under any circumstances.
F
False
EQ
Equal
OGT
Ordered Greater Than
OGE
Ordered Greater Than or Equal
OLT
Ordered Less Than
OLE
Ordered Less Than or Equal
OGL
Ordered Greater or Less Than
OR
Ordered
UN
Unordered
UEQ
Unordered or Equal
UGT
Unordered or Greater Than
UGE
Unordered or Greater or Equal
ULT
Unordered or Less Than
ULE
Unordered or Less or Equal
NE
Not Equal
T
True
Note: The following conditional tests set the BSUN bit in the status register exception byte if the NAN condition code bit is set when a
conditional instruction is executed.
SF
Signaling False
SEQ
Signaling Equal
GT
Greater Than
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