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參數(shù)資料
| 型號： | TS8882VF20 |
| 文件頁數(shù)： | 31/42頁 |
| 文件大?。?/td> | 1703K |
| 代理商： | TS8882VF20 |
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31
TS68882
2119A
–
12/01
Size (SIZE)
This active-low input signal is used in conjunction with the A0 pin to configure the TS 68882 for
operation over an 8-, 16-, or 32-bit system data bus. When the TS 68882 is configured to oper-
ate over a 16-or 32-bit system data bus, both the SIZE and A0 pins are strapped high and/or
low as listed in Table 11.
Address Strobe
(AS)
This active-low input signal indicates that there is a valid address on the address bus, and
both the chip select (CS) and read/write (R/W signal lines are valid).
Chip Select (CS)
This active-low input signal enables the main processor access to the TS 68882 coprocessor
interface registers. When operating the TS 68882 as a peripheral processor, the chip select
decode is system dependent (i.e., like the chip select on any peripheral). The CS signal must
be valid (either asserted or negated) when AS is asserted. Refer to CHIP SELECT TIMING for
further discussion of timing restrictions for this signal.
Read/Write (R/W)
This input signal indicates the direction of a bus transaction (read/write) by the main proces-
sor. A logic high (1) indicates a read from the TS 68882, and a logic low (0) indicates a write to
the TS 68882. The R/W signal must be valid when AS is asserted.
Data Strobe (DS)
This active-low input signal indicates that there is valid data on the data bus during a write bus
cycle.
Data Transfer and Size
Acknowledge
(DSACK0, DSACK1)
These active-low, three-state output signals indicate the completion of a bus cycle to the main
processor. The TS 68882 asserts both the DSACK0, and DSACK1 signals upon assertion of
CS.
If the bus cycle is a main processor read, the TS 68882 asserts DSACK0 and DSACK1 signals
to indicate that the information on the data bus is valid. (Both DSACK signals may be asserted
in advance of the valid data being placed on the bus). If the bus cycle is a main processor
write to the TS 68882, DSACK0 and DSACK1 are used to acknowledge acceptance of the
data by the TS 68882.
The TS 68882 also uses DSACK0 and DSACK1 signals to dynamically indicate to the TS
68020/TS 68030 the
“
port
”
size (system data bus width) on a cycle-by-cycle basis. Depending
upon which of the two DSACK pins are asserted in a given bus cycle, the TS 68020/TS 68030
assumes data has been transferred to/from an 8-, 16-, or 32-bit wide data port. Table 12 lists
the DSACK assertions that are used by the TS 68882 for the various bus cycles over the vari-
ous bus cycles over the various system data bus configurations.
Table 12 indicates that all accesses over a 32-bit bus where A4 equals zero are to 16-bit reg-
isters. The TS 68882 implements all 16-bit coprocessor interface registers on data lines D16-
D13 (to eliminate the need for on-chip multiplexers); however, the TS 68020/TS 68030
expects 16-bit registers that are located in a 32-bit port at odd word addresses (A1 = 1) to be
implemented on data lines D0-D15. For accesses to these registers when configured for 32-bit
bus operation, the TS 68882 generates DSACK signals as listed in Table 12 to inform the TS
68020/TS 68030 of valid data on D16-D31 instead of D0-D15.
An external holding resistor is required to maintain both DSACK0 and DSACK1 high between
bus cycles. In order to reduce the signal rise time, the DSACK0 and DSACK1 lines are actively
pulled up (negated) by the TS 68882 following the rising edge of AS or DS and both DSACK
lines are then three-stated (placed in the high-impedance state) to avoid interference with the
next bus cycle.
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