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| 型號： | TS8882VF20 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 1703K |
| 代理商： | TS8882VF20 |
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18
TS68882
2119A
–
12/01
Functional
Description
The Coprocessor
Concept
The TS 68882 functions as a coprocessor in systems where the TS 68020 or TS 68030 is the
main processor via the TS 68000 coprocessor interface. It functions as a peripheral processor
in systems where the main processor is the TS 68000, TS 68010.
The TS 68882 utilizes the TS 68000 Family coprocessor interface to provide extension of the
TS 68020 /TS 68030 registers and instruction set in a manner which is transparent to the pro-
grammer. The programmer perceives the MPU/FPCP execution model as if both devices are
implemented on one chip.
A fundamental goal of the TS 68000 Family coprocessor interface is to provide the program-
mer with an execution model based upon sequential instruction execution by the TS 68020/TS
68030 and the TS 68882. For optimum performance, however, the coprocessor interface
allows concurrent operations in the TS 68882 with respect to the TS 68020/TS 68030 when-
ever possible. In order to simplify the programmer
’
s model, the coprocessor interface is
designed to emulate, as closely as possible, non-concurrent operation between the TS
68020/TS 68030 and the TS 68882.
The TS 68882 is s non-DMA type coprocessor which uses a subset of the general purpose
coprocessor interface supported by the TS 68020/TS 68030. Features of the interface imple-
mented in the TS 68882 are as follows:
The main processor(s) and TS 68882 communicate via standard TS 68000 bus cycles
The main processor(s) and TS 68882 communications are not dependent upon the
instruction sets or internal details of the individual devices (e.g., instruction pipes or
caches, addressing modes)
The main processor(s) and TS 68882 may operate at different clock speeds
TS 68882 instructions utilize all addressing modes provided by the main processor; all
effective addresses are calculated by the main processor at the request of the
coprocessor
All data transfers are performed by the main processor at the request of the TS 68882;
thus memory management, bus errors, address errors, and bus arbitration function as if
the TS 68882 instructions are executed by the main processor
Overlapped (concurrent) instruction execution enhances throughput while maintaining the
programmer
’
s model of sequential instruction execution
Coprocessor detection of exceptions which require a trap to be taken are serviced by the
main processor at the request of the TS 68882 thus exception processing functions as if
the TS 68882 instructions were executed by the main processor
Support of virtual memory/virtual machine systems is provided via the FSAVE and
FRESTORE instructions
Up to eight coprocessors may reside in a system simultaneously: multiple coprocessors of
the same type are also allowed
Systems may use software emulation of the TS 68882 without reassembling or relinking
user software
The TS 68882 programming model is shown in Figure 10 through 15, and consists of the
following:
Eight 80-bit floating-point data registers (FP0-FP7). These registers are analogous to the
integer data registers (D0-D7) and are completely general purpose (i.e., any instruction
may use any register)
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