參數(shù)資料
型號(hào)： TSB12LV01B-EP
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式
文件頁數(shù)： 13/106頁
文件大?。?/td> 605K
代理商： TSB12LV01B-EP
1
–
5
1.5
The terminal functions are described in Table 1
–
1.
Terminal Functions
Table 1
–
1. Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Microcontroller/Microprocessor Interface
BCLK
6
I
Microinterface clock. Maximum frequency is 60 MHz. In the ColdFire mode,
BCLK is the same as CLK, which is the clock-input signal to the ColdFire.
COLDFIRE
12
I
ColdFire mode. To operate in this mode, COLDFIRE must be asserted high.
LENDIAN
75
I
Little-endian mode for the microinterface. When this terminal is pulled up, the
data on MD0
–
MD15 will be byte-swapped to little endian byte format before it is
written to the CFR or FIFO and after it is read from the CFR or FIFO.
MA0
–
MA6
24
–
21
19
–
17
I
Microcontroller address bus. MA0 is the most significant bit (MSB) of these 7 bits.
M8BIT/SIZ0
13
I
Configuration bit for microinterface. If the microinterface is 8 bits wide, this
terminal must be pulled up to the supply voltage. In ColdFire mode, this terminal
represents burst SIZ0.
MCMODE/SIZ1
14
I
Mode bit for microinterface. If the microinterface wants to communicate in a
handshake manner this terminal must be pulled up to the supply voltage. When
the ColdFire mode terminal (12) is high, this terminal represents burst SIZ1.
MCA
4
O
Microinterface cycle acknowledge. When asserted low, MCA signals an
acknowledge of the microcontroller cycle from the TSB12LV32.
MCS
7
I
Microinterface cycle start. When asserted low, MCS signals the beginning of a
microcontroller operation to the TSB12LV32.
MDINV
11
I
Microinterface data invariant mode. This terminal is meaningful only when
LENDIAN (75) is high. When asserted high, the microinterface operates in the
data invariant mode. When low, the microinterface operates in address invariant
mode.
MD0
–
MD15
99
–
96
94
–
91
89
–
86
84
–
81
I/O
Microinterface bidirectional data bus. MD0 is the most significant bit. However,
byte significance is dependent on the state of the LENDIAN and MDINV
terminals.
MWR
8
I
Microcontroller read/write indicator. When asserted high, MWR indicates a read
access from the TSB12LV32. When asserted low, MWR indicates a write access
to the TSB12LV32.
TEA
3
O
Transfer error acknowledge. This active-low signal is asserted low for one BCLK
cycle whenever there is an illegal transfer request by the microcontroller (i.e.,
requested data transfer size is unsupported or MCS is asserted low for more than
one BCLK cycle in ColdFire mode).
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