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參數(shù)資料
| 型號(hào)： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數(shù)： | 16/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01B-EP |
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1
–
8
1.5.1
STAT0, STAT1 and STAT2 terminals can be independently programmed to show one of fourteen possible
internal hardware status. The controls for the STAT terminals are in the
Diagnostic
register at address 20h
of the CFR register. STAT0 is controlled by STATSEL0(bits 16
–
19), STAT1 is controlled by bits
STATSEL1(bits 20
–
23), and STAT2 is controlled by STATSEL2 (bits 24
–
27). Refer to Table 1
–
2 for
programming the STAT terminals.
STAT0, STAT1, and STAT2 Programming
Table 1
–
2. STAT Terminals Programming
STATSEL0,
STATSEL1, or
STATSEL2
STAT0/STAT1/STAT2
DESCRIPTION
0
0
0
0
Reserved
Reserved
0
0
0
1
ATFFULL
ATF is full. Bit 12 in CFR at 30h.
0
0
1
0
Bus Reset
1394 Bus reset. Bit 3 in CFR at 0Ch
0
0
1
1
Arbitration reset gap
Bit 26 in CFR at 0Ch
0
1
0
0
CYCLEOUT
Cycle out. This is the link
’
s cycle clock. It is based on the timer
controls and the received cycle-start messages.
0
1
0
1
RXDMPKT
Packet received to DM interrupt. Activated at the end of a received
packet. Bit 9 in CFR at 0Ch
0
1
1
0
RXGRFPKT
Packet received to GRF interrupt. Activated at the end of a received
packet. . Bit 6 of CFR at 0Ch
0
1
1
1
BX_BUSY
Byte busy. This represents the OR of bits 0
–
3 of CFR at 20h
1
0
0
0
SUBGP
Subaction gap. Activated upon detection of a subaction gap. Bit 27
in CFR at 0Ch
1
0
0
1
CYCLE_DONE
Cycle done. Indicates the end of the isochronous period. This
happens when a subaction gap has been detected.
1
0
1
0
ATSTARTED
(default setting for STAT1)
Activated when an asynchronous packet transfer has started from
the ATF. Bit 5 in CFR at 0Ch
1
0
1
1
DMACKERR
DM acknowledge was not Complete. Bit 17 in CFR at 0Ch
1
1
0
0
DMEN
DM enable. Bit 26 in CFR at 04h
1
1
0
1
GRFEMPTY
(default setting for STAT2)
GRF is empty. Bit 15 in CFR at 30h.
1
1
1
0
Reserved
Reserved
1
1
1
1
Reserved
Reserved
1.6
Ordering Information
TEMPERATURE
ORDERING NUMBER
TOP-SIDE MARKING
PACKAGE
–
40
°
C to 110
°
C
TSB12LV32TPZEP
TSB12LV32TEP
100-Terminal PQFP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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