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| 型號： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數(shù)： | 76/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV01B-EP |
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6
–
1
6 FIFO Memory Access
Access to all FIFO memories is fundamentally the same, only the addresses to where the write is made
changes. Figure 6
–
1 shows the FIFO-address access map. The FIFO is separated into an asynchronous
transmit FIFO (ATF) and a general receive FIFO (GRF), each of 517 quadlets (2 Kbytes). Since
asynchronous packets may also be transmitted through the data mover port and the ATF always has priority
and its data wil be transmitted first.
0
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 21 2223 24 25 26 27 28 29 30 31
50h
ATF_First
ATF_Continue
ATF_Continue & Update
GRF Data
54h
58h
5Ch
60h
64h
68h
ATF_First_Update
ATF_Burst_Write
Reserved
Figure 6
–
1. TSB12LV32 Controller-FIFO-Access Address Map
6.1
The suffix _First denotes a write to the FIFO location where the first quadlet of a packet should be written
when the writer wants to transmit the packet. The first quadlet is held in the FIFO until a quadlet is written
to an update location. The suffix _Continue denotes a write to the FIFO location where the second through
n-1 quadlets of a packet should be written. The second through n-1 quadlets are held in the FIFO until a
quadlet is written to an update location. The suffix_Continue & Update denotes a write to the FIFO location
where the last quadlet of a multiple quadlet packet should be written.
6.2
ATF Access
The procedure for accessing the ATF for a quadlet write operation is accomplished in three successive
steps. To ensure that an ATF underflow condition does not occur, loading of the ATF in the following manner
is highly recommended:
General
First Quadlet of the Packet
Successive (N
–
1) Quadlets of the Packet
Last (Nth) Quadlet of the Packet
Figure 6
–
2. Asynchronous Packet With N Quadlets (ATV Loading Operation)
Each quadlet can be written into the ATF register on byte (8-bit) boundary or word (16-bit) boundary. To write
to the ATF in a byte fashion, the following steps should be followed:
Step 1:
Writing the first quadlet of the packet:
a)
Write the first 8-bits of the quadlet to ATF location 50h.
b)
Write the second 8-bits of the quadlet to ATF location 51h.
c)
Write the third 8-bits of the quadlet to ATF location 52h.
d)
Write the fourth 8-bits of the quadlet to ATF location 53h.
The data is not yet confirmed for transmission.
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PDF描述 |
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| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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