參數(shù)資料
型號: TSB12LV01B-EP
英文描述: FPGA (Field-Programmable Gate Array)
中文描述: 軍事增強塑料的高性能1394 3.3鏈路層電信。嵌入式
文件頁數(shù): 27/106頁
文件大?。?/td> 605K
代理商: TSB12LV01B-EP
2
11
BIT
NUMBER
DESCRIPTION
DIR
FUNCTION
BIT NAME
27
SUBGP
Subaction gap
R/W
When SUBGP is set, the serial bus has been idle for a subac-
tion gap time (fair-gap). This bit can be set only when the
REGRW bit has been set in the diagnostics register at 20h.
28
30
RESERVED
RESERVED
31
IARBFL
Isochronous
arbitration failed
R/W
When IARFL is set, the arbitration to send an isochronous
packet has failed.
2.2.5
Cycle Timer Register at 14h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
SECOND COUNT
CYCLE OFFSET
CYCLE COUNT
This register must be written to as a quadlet. The power-up reset value of this register =
0000_0000
h
BIT NUMBER
BIT NAME
FUNCTION NAME
DIR
DESCRIPTION
0
6
Seconds_count
Seconds count
R/W
1-Hz cycle timer counter
7
19
Cycle_count
Cycle count
R/W
8,000-Hz cycle timer counter
20
31
Cycle_offset
Cycle offset
R/W
24.576-MHz cycle timer counter
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相關代理商/技術參數(shù)
參數(shù)描述
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TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray