參數(shù)資料
型號(hào)： TSB12LV01B-EP
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式
文件頁數(shù)： 65/106頁
文件大?。?/td> 605K
代理商： TSB12LV01B-EP
5
–
9
5.1.4.1
In this mode, the header information is first loaded into the header0
–
header3 registers through the
microcontroller interface. The headers will subsequently be automatically inserted into the data once the
data mover starts streaming it through to the link core transmitter logic. The following steps further illustrate
the process:
Asynchronous Packet Transmit With Automatic Header Insertion
Step 1:
Asynchronous header quadlets (3 quadlets in quadlet receive mode and 4 quadlets in block
receive mode) are loaded into header0
–
header3 registers through a write operation from
the microcontroller interface. Loading one header requires a single write operation.
Step 2:
Header quadlets are forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Asynchronous packet is sent to the 1394 bus through the Phy.
NOTE:
The data coming through the data mover port is typically supplied by an external
fast memory block (i.e., FIFO, DRAM). This external memory logic may begin
transmitting data through to the data mover port exactly one DMCLK cycle after the
DMPRE output pin on the GP2Lynx is asserted high.
CFR REGISTER
Step 4
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Quadlet#0
Packet sent
to 1394 bus
through the
Phy
Header1 Register at 3Ch
Quadlet#1
Header2 Register at 40h
Quadlet#2
Header3 Register at 42h
Quadlet#3
Loaded only in
Block Receive
Data
Mover
Port
Step 3 (packet data)
Step 2
Step 3
Step 1
Headers
loaded
Micro-
controller
Interface
Step 1
Write
Header
Quadlets
Figure 5
–
11. Asynchronous Transmit With Auto Header Insertion
相關(guān)PDF資料
PDF描述
TSB12LV01BPZ FPGA (Field-Programmable Gate Array)
TSB12LV26-EP 672-pin FineLine BGA
TSB12LV22PZP OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26PZ OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB14AA1 FPGA (Field-Programmable Gate Array)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01BIPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BIPZTEP 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*