參數(shù)資料
型號(hào): TSB12LV01B-EP
英文描述: FPGA (Field-Programmable Gate Array)
中文描述: 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式
文件頁數(shù): 36/106頁
文件大?。?/td> 605K
代理商: TSB12LV01B-EP
2
20
2.2.17
Trailer Register at 48h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
L
28
NUMBER OF QUADLETS
ACKCODE
SPD
L
The power-up reset value of this register =
0000_0000
h
.
BIT
NUMBER
BIT NAME
FUNCTION
NAME
DIR
DESCRIPTION
0
1
RESERVED
RESERVED
2
15
numofQuadlets
Number of
Quadlets
R/W
Total number of quadlets in the current packet (data payload
and header quadlets only)
16
18
19
23
RESERVED
AckCode
RESERVED
Acknowledge
Code
R/W
This 5-bit field holds the acknowledge code sent by the
receiver for the current packet (see Note following the table):
Ack Code
00000
Name
Reserved
00001
Ack_complete
00010
Ack_pending
00011
Reserved
00100
Ack_busy_X
00101
Ack_busy_A
00110
Ack_busy_B
00111
01100
Reserved
01101
Ack_data_error
01110
Ack_type_error
01111
Reserved
10000
No ack received
These codes are add-
h li k l
ed by the link layer
and are not part of the
IEEE 1394 1995
specification.
10001
Ack too long
10010
Ack too short
10011
11111
Reserved
24
25
RESERVED
RESERVED
26
27
SPD
Speed Code
R/W
The spd field indicates the speed at which the current packet
was sent.
00 => 100 Mbit/s, 10 = > 400 Mbits/s,
01 => 200 Mbit/s, 11 is undefined.
28
29
RESERVED
RESERVED
NOTE:
The acknowledge code specified by the IEEE 1394-1995 specification is a 4-bit
field. The AckCode field in this register is a 5-bit field. The TSB12LV32 logic core
is able to provide (specifiy) three additional ack codes, which are not part of the
original specification. The ack codes are 10000, 10001, and 10010.
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