- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365967 > TSB12LV01B-EP FPGA (Field-Programmable Gate Array) PDF資料下載
參數(shù)資料
| 型號： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數(shù)： | 60/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01B-EP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當(dāng)前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
5
–
4
5.1
The data mover has eight modes of operation. There are four modes for transmit and four modes for receive.
Data Mover Data Flow Diagram
Definitions
Data mover port configured to operate in transmit mode means that the packet data is received
through the data mover port and forwarded (unbuffered) to the link core transmit logic to be sent
to the physical layer device (Phy), which will, in turn,
transmit
the data onto the 1394 bus.
Data mover port configured to operate in receive mode means that the packet data is
received
by the link core receive logic from the 1394 bus through the Phy. The data is then routed by the
link core to the data mover port without any internal buffering.
5.1.1
In all the isochronous receive modes, the packet header information is always loaded into the header
registers. The packet header quadlet is loaded into the Header0 register at 38h and the packet trailer quadlet
is loaded into the trailer register at 48h.
Isochronous Receive
5.1.1.1
Isochronous Packet Receive Without Header and Trailer
Step 1:
Isochronous packet is received through the receiver logic of the link core
Step 2:
The packet header is stripped off from the packet and loaded into the header0 register at
38h.
Step 3:
Packet data (payload only) is routed directly to the DM port without any buffering.
Step 4:
Trailer quadlet is loaded into the trailer register at 48h
CFR REGISTER
Step 1
Data
Mover
Port
Header0 Register at 38h
Trailer Register at 48h
LINK CORE
Transmitter
Receiver
Step 2
Step 4
Step 3 (Packet Data)
Packet received from
1394 bus through the
Phy
Figure 5
–
5. Isochronous Receive Without Header and Trailer
5.1.1.2
Isochronous Packet Receive With Header and Trailer
Step 1:
Isochronous packet is received through the receiver block of the link core.
Step 2:
The header quadlet is both loaded into the header0 register at 38h and routed to the DM
port without any buffering.
Step 3:
Packet data (payload only) is sent directly through the DM port only.
Step 4:
Trailer quadlet is loaded into the trailer register at 48h. It is also forwarded to the DM port.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。