參數(shù)資料
型號(hào)： TSB12LV01B-EP
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式
文件頁(yè)數(shù)： 15/106頁(yè)
文件大?。?/td> 605K
代理商： TSB12LV01B-EP
1
–
7
Table 1
–
1. Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Miscellaneous Functions
CONTNDR
65
I/O
Contender. When asserted high, this terminal tells the link that this node is a
contender for isochronous resource manager (IRM) or bus manager functions.
The state of the CONTNDR must match the state of the Phy contender terminal for
1394-1995 compliant Phys, and the Phy register bit for 1394.A compliant Phys.
This terminal defaults to being an input on power up. After power up, the value of
this terminal may be driven internally by the CTNDRSTAT bit (bit#12 at 08h)
CYCLEIN
76
I
Cycle in. This input is an optional external 8-kHz clock used as the isochronous
cycle clock. It should only be used if attached to the cycle-master node. It is
enabled by the cycle source bit and should be tied high when not used.
CYSTART
2
O
Isochronous cycle start indicator. CYSTART signals the beginning an isochronous
cycle by pulsing for one DMCLK period.
DIRECT
79
I
Isolation terminal. When this terminal is asserted high, no isolation is present
between the TSB12LV32 and the Phy. When low, bus holder isolation becomes
active.
GND
5, 25, 30,
45, 57, 73,
78, 90,
100
Ground reference
INT
1
O
Interrupt. NOR of all internal interrupts.
9
I
STAT0
–
STAT2
54
–
56
O
General status outputs. STATn is the output signal selected with the CFR at
address 20h.
TESTMODE
16
I
This terminal is used to place the TSB12LV32 in the test mode. In normal
operation, this terminal must be tied to ground.
VDD5V
10, 35, 85
5 V (
±
0.5V) supply voltage for 5-V tolerant inputs. Only the Phy/link interface side
of the TSB12LV32 is
not
5-V tolerant. Tie this terminal to the 3.3-V supply voltage if
the TSB12LV32 is not connected to any devices driving 5-V signals. Tie this
terminal to the 5-V supply voltage if the TSB12LV32 is connected to any devices
driving 5-V signals. This terminal is only used to make inputs 5-V tolerant, it is not
used for any outputs.
VDD
15, 20, 40,
47, 68, 71,
80, 95
3.3 V (
±
0.3 V) supply voltage
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01BIPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BIPZTEP 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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