參數(shù)資料
型號: TSB12LV01B-EP
英文描述: FPGA (Field-Programmable Gate Array)
中文描述: 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式
文件頁數(shù): 18/106頁
文件大?。?/td> 605K
代理商: TSB12LV01B-EP
2
2
Table 2
1. Configuration Register (CFR) Map
40h
44h
38h
3Ch
Header0
Header1
Header2
Asynchronous
Retry
Header3
NUMBER OF QUADLETS
ASYNC RETRY COUNT
RETRY INTERVAL
ACKCODE
SPD
Trailer
4Ch
48h
L
L
1Ch
20h
24h
28h
2Ch
B
B
B
B
B
B
R
R
R
A
A
G
30h
34h
Diagnostic
Phy Access
Reserved
FIFO Status
Bus Reset
Maint_Control
PHYRGAD
PHYRGDATA
PHYRXAD
PHYRXDATA
N
B
B
STATSEL0
STATSEL1
STATSEL2
W
A
G
C
ATACK
GRFUSED
R
C
IRMNODEID
BUS NUMBER
NODE NUMBER
E
E
N
F
N
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
00h
P
S
A
S
R
DM Control
Interrupt
Isochronous
Port
P
S
C
C
C
C
C
04h
0Ch
10h
14h
18h
28
I
A
S
H
08h
I
A
P
Interrupt
Mask
Cycle Timer
VERSION
(711538A0h)
0
1
1
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
E
B
H
A
DMACK
D
A
A
D
D
C
D
S
R
R
C
C
F
R
F
P
B
T
R
E
E
B
B
B
D
F
C
C
C
C
CODE
SID
C
I
I
C
D
R
A
T
M
D
F
P
S
A
S
R
P
S
C
C
C
C
C
I
A
S
H
I
A
P
C
D
R
A
T
M
D
F
SECONDS COUNT
CYCLE COUNT
Control
T
T
M
ISYNCRCVN
I
MSB
LSB
L
L
E
NOTES: A. All dark gray areas (bits) are reserved bits.
B. All light gray areas are read-only bits. All remaining are read/write bits.
PACKET PER BLOCK
IRPORT1
ATFAVAIL
NODECNT
IRPORT2
ACK
CYCLE OFFSET
PING VALUE
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