參數(shù)資料
型號(hào)： TVP3010-135
廠商： Texas Instruments, Inc.
英文描述： Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
中文描述： 硬件光標(biāo)，伽瑪校正貴賓（135MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板）
文件頁(yè)數(shù)： 15/100頁(yè)
文件大小： 571K
代理商： TVP3010-135
2–1
2 Detailed Description
The 32-bit TVP3010 is pin compatible with the TLC34076 but offers advanced features. To facilitate the
enhanced functionality, some terminals have dual functions. The dual-function terminals are controlled by
the configuration register discussed in Section 2.16.1. At reset, all terminals default to the TLC34076
terminal functions.
2.1
MPU Interface
The processor interface is controlled via read and write strobes (RD, WR), three register-select terminals
[RS(0–2)], and the 8/6-select terminal. The 8/6 terminal is used to select between an 8- or 6-bit-wide data
path to the color-palette RAM and is provided in order to maintain compatibility with the IMSG176. Since
the 8/6 [OVS] terminal is a dual-function terminal, two bits are provided in the configuration register to control
this function. Configuration register bit 1 determines whether the 8/6 [OVS] terminal operates as 8/6 or OVS.
If configuration register bit 1 is set to logic 0 (default), then 8/6 operation is controlled by the terminal. With
8/6 held low, data on the lowest six bits of the data bus are internally shifted up by two bits to occupy the
upper six bits at the output multiplexer and the bottom two bits are then zeroed. This operation is carried
out in order to utilize the maximum range of the DACs.
The direct register map is shown in Table 2–1. Extended registers can be accessed through the index
register. The index register map is shown in Table 2–2. In general, the index register must first be loaded
with the target address value. Successive reads or writes from and to the data register then access the target
location. The MPU interface operates asynchronously, with data transfers being synchronized by internal
logic.
NOTE:
RS3 is a don’t care for register addressing but is used as the PSEL input. See
Section 2.6.
Table 2–1. Direct Register Map
RS2
RS1
RS0
REGISTER ADDRESSED BY MPU
R/W
DEFAULT (HEX)
0
0
0
Palette-Address Register – Write Mode
R/W
XX
0
0
1
Color-Palette Holding Register
R/W
XX
0
1
0
Pixel Read Mask
R/W
FF
0
1
1
Palette-Address Register – Read Mode
R/W
XX
1
0
0
Reserved
XX
1
0
1
Reserved
XX
1
1
0
Index Register
R/W
XX
1
1
1
Data Register
R/W
XX
Table 2–2. Indirect Register Map (Extended Registers)
INDEX REGISTER
(HEX)
R/W
DEFAULT
(HEX)
REGISTER ADDRESSED
BY INDEX REGISTER
00
R/W
00
Cursor-Position X LSB
01
R/W
00
Cursor-Position X MSB
02
R/W
00
Cursor-Position Y LSB
03
R/W
00
Cursor-Position Y MSB
NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate
from that specified. Reserved-undefined registers are nonexistent locations on
the register map.
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