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參數(shù)資料
| 型號(hào)： | TVP3010-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標(biāo)，伽瑪校正貴賓（135MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 19/100頁 |
| 文件大?。?/td> | 571K |
| 代理商： | TVP3010-135 |
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2–5
2.3
The TVP3010 VIP provides a maximum of five clock inputs. One of them (CLK0) is dedicated as a TTL input.
The other four can be selected as either two differential ECL input or two extra TTL inputs. The TTL inputs
can be used for video rates up to 140 MHz. The dual-mode clock input (ECL/TTL) is primarily an ECL input
but can be used as TTL-compatible inputs if the input-clock-selection register is so programmed. The clock
source used at power up is CLK0; an alternative source can be selected by software during normal
operation. This chosen clock input can be used unmodified as the dot clock (representing pixel rate to the
monitor). Alternatively, if the input-clock-selection register is programmed to use the internal frequency
doubler, the chosen clock source is used as a reference for multiplication. The device also allows for user
programming of RCLK, SCLK and VCLK outputs (reference, shift and video clocks) by using the
output-clock-selection register. The input-clock- and output-clock-selection registers are shown in Tables
2–4 and 2–5 and are located in the indirect register map (see Table 2–2).
Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation
The ECL inputs can be used as a differential or single-ended inputs. If CLK1 or CLK3 is used as a
single-ended ECL input, CLK2 or CLK4 needs to be externally terminated to set the input common-mode
signal level. This can be done with a simple resistor divided, as is the case with fully differential ECL. Care
needs to be taken when choosing the resistor values to ensure that the dc level on CLK2 or CLK4 is in the
middle of the CLK1 or CLK3 ECL-input signal range.
2.3.1
RCLK, SCLK, VCLK
The TVP3010 VIP provides user-programmable reference clock (RCLK), shift clock (SCLK), and video
(VCLK) clock outputs that can be set as divisions of the dot clock. RCLK is a continuously running reference
clock and is not disabled during blank. RCLK can be selected as divisions of 1, 2, 4, 8, 16, 32 or 64 of the
dot clock (see Table 2–5). It is provided as a clock reference and is typically connected back to the LCLK
input to latch pixel-port data. Since pixel-port data is latched on the rising edge of LCLK, the RCLK frequency
must be set as a function of the desired multiplexing ratio (that depends on the pixel bus width and number
of bit planes). See Section 2.4 and Table 2–6.
SCLK is the same as RCLK but disabled during the blank active period. SCLK is designed to be used as
the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and
held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing
is discussed in Section 2.3.2 and illustrated in Figures 2–2 through 2–5.
VCLK is designed to be used as the timing reference by the graphics processor or other custom-designed
control logic to generate the graphics system control signals (SYSBL, HSYNC, and VSYNC). VCLK can be
selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock and can also be held at logic 1 (see Table 2–5).
The default setup is VCLK held at logic 1 since it is not used in VGA pass-through mode. Since these control
signals are sampled by VCLK, VCLK must be enabled for these to function properly (see Figures 2–2
through 2–5).
Even though RCLK/SCLK and VCLK can be selected independently, there is still a relationship between
the two as discussed below. Many system considerations have been carefully covered in their design,
leaving maximum freedom to the user.
Internally, RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising
edge of the dot clock. Therefore, when VCLK is enabled, it is naturally in phase with RCLK and SCLK as
shown in Figure 2–1.
Normally, the video control signal inputs HSYNC, VSYNC, and SYSBL are latched on the falling edge of
VCLK when in a non-VGA mode. If the configuration register is programmed for opposite VCLK polarity,
these video control signals are latched on the rising edge of VCLK.
The internal clock counter is initialized any time the output-clock-selection register is written with 3F (hex).
This provides a simple mechanism to synchronize multiple palettes or system devices by providing a known
phase relationship for the various system clocks. It is left up to the user to provide some means of disabling
the dot clock input to the part while this reset is occurring if multiple parts are to be synchronized.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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| TVP3010-135MGAB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-85FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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