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| 型號： | TVP3010-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標(biāo)，伽瑪校正貴賓（135MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 94/100頁 |
| 文件大?。?/td> | 571K |
| 代理商： | TVP3010-135 |
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E–8
Cursor RAM Address (LS, MS) Register
These registers are used to specify the address of where to write or read sprite cursor data from. The linear
addressing scheme is depicted in Figure 4 of section 2.5.1. The Cursor RAM register is made up of the
Cursor RAM LS (CRLS) and the Cursor RAM MS (CRMS). They are not initialized and may be written to
by the MPU at any time.
CRLSL and CRMS are cascaded to form a 10–bit Cursor RAM Address register. Bits D2–D7 of CRMS are
always a logical zero.
Table J–14.
Cursor RAM MS Address
Cursor RAM LS Address
(CRMS)
(CRLS)
Data bit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Address
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Index = 09h
Index = 08h
Index = 09 (hex)
Index = 08 (hex)
Values from 0000 (hex) to 03FF (hex) may be written into the Cursor RAM Address register.
Note that when the cursor RAM address is to be written, both registers must be written with the Cursor RAM
LS Address being the first.
Cursor RAM Data Register
This register is used to read and write the contents of the sprite cursor locations whose address is specified
in the Cursor RAM Address registers. The data read from or written to this register will contain 4 pixels of
information, 2 bit planes per cursor pixel (see Figure 4 & section 2.5.1). The register is not initialized and
may be written to or read from by the MPU at any time. The Sprite cursor data format is shown below.
Table J–15.
Cursor RAM Data
Data bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
P1
3
P0
3
P1
2
P0
2
Index = 0Ah
P1
1
P0
1
P1
0
P0
0
Values from 00 (hex) to 3F (hex) may be written into the Cursor RAM Data register.
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