參數(shù)資料
型號: TVP3010-135
廠商: Texas Instruments, Inc.
英文描述: Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標,伽馬校正,視頻接口調(diào)色板)
中文描述: 硬件光標,伽瑪校正貴賓(135MHz,高/寬光標,伽馬校正,視頻接口調(diào)色板)
文件頁數(shù): 79/100頁
文件大?。?/td> 571K
代理商: TVP3010-135
B–1
Appendix B
RCLK Frequency < VCLK Frequency
The VCLK, RCLK, and SCLK outputs generated by the TVP3010 VIP are free-running clocks. The
video-control signals (i.e., HSYNC, VSYNC, and SYSBL) are normally generated from VCLK, and a fixed
relationship between video-control signals and VCLK can be expected. The TVP3010 samples and latches
the blank internal input on the falling edge of VCLK. It then looks at the internal RCLK signal to determine
when to enable or disable SCLK at the output terminal. The decision is determined when the RCLK
frequency is greater than or equal to the VCLK frequency. However, when the RCLK frequency is less than
the VCLK frequency, the appearance of the SCLK waveform at the output terminal (when SYSBL is sampled
low on the falling edge of VCLK) can vary (see Figures B–1 and B–2).
To avoid this variation in the SCLK output waveform, the RCLK and VCLK frequencies should be chosen
so that HTOTAL is evenly divisible by the ratio of the VCLK frequency to the RCLK frequency:
remainder of [ HTOTAL/(VCLK frequency/RCLK frequency)] = 0
For example, if HTOTAL is even, VCLK frequency = dot clock frequency/8 and RCLK frequency = dot clock
frequency/16. Then the above formula is satisfied. NOTE: When HTOTAL starts at zero, then the formula
becomes:
remainder of [ (HTOTAL + 1)/(VCLK frequency/SCLK frequency) ] = 0.
VCLK
SYSBL
At Input
Terminal
RCLK
SCLK
Figure B–1. VCLK and SCLK Phase Relationship (Case 1)
VCLK
SYSBL
At Input
Terminal
RCLK
SCLK
Figure B–2. VCLK and SCLK Phase Relationship (Case 2)
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