參數(shù)資料
型號(hào): TVP3010-135
廠商: Texas Instruments, Inc.
英文描述: Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
中文描述: 硬件光標(biāo),伽瑪校正貴賓(135MHz,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
文件頁數(shù): 46/100頁
文件大?。?/td> 571K
代理商: TVP3010-135
2–32
2.9
The TVP3010 palette provides several functions that enable system testing and verification. These are
detailed below.
Test Functions
2.9.1
A 16-bit cyclic redundancy check (CRC) is provided so that video data integrity can be verified at the input
to the DACs. The CRC is updated on the second horizontal sync rising edge during vertical retrace and is
only calculated on the active screen area; i.e., active blank stops the calculation. The CRC can be performed
on any of the 24 data lines that enter the DACs and is controlled by the CRC-control register (CRCC
bits 0–4). Values from 0 to 23 may be written to this register to select between the 24 different DAC data
inputs. Value 0 corresponds to DAC data red 0 (LSB), value 7 to red 7 (MSB), value 8 to green 0 (LSB), value
15 to green 7 (MSB), value 16 to blue 0 (LSB), and value 23 to blue 7 (MSB). The 16-bit remainder that is
calculated on the individual DAC data line can be read from the CRCLSB and CRCMSB registers. See
Table 2–2 for the indirect register map address. See Sections 2.16.15 and 2.16.16 for the CRC register bit
definitions.
16-Bit CRC
As long as the display pattern for each screen remains fixed, the CRC result should remain constant. If the
CRC result changes, an error condition should be assumed. Since the CRC is calculated using the common
CRC–16 polynomial (X
16
+ X
15
+ X
2
+ 1), the user can calculate and store the CRC remainder for a test
screen in software and compare this to the TVP3010-calculated CRC remainder to verify data integrity.
2.9.2
The TVP3010 provides a SENSE output to support system diagnostics. The MUXOUT [SENSE] terminal
can be configured as the SENSE output by programming bit 3 of the configuration register to logic 1. SENSE
can be used to determine the presence of the CRT monitor or verify that the RGB termination is correct.
SENSE is a logic L if one or more of the DAC outputs exceeds the internal comparator voltage of 350 mV.
The internal 350-mV reference has a tolerance of
±
50 mV when using an external 1.235-V reference. If the
internal voltage reference is used, the tolerance is higher.
Sense Comparator Output and Test Register
The sense comparators are also integrated with the sense-test register so that the comparison results for
the red, green, and blue comparators can be read independently through the 8-bit microinterface. When the
sense-test register (STR) is read, the results are indicated in the bit positions as shown below.
STR BITS
D7
D6
D5
D4
D3
D2
D1
D0
Data
0
0
0
0
0
R
G
B
where:
R = logic 1 if IOR > 350 mV
G = logic 1 if IOG > 350 mV
B = logic 1 if IOB > 350 mV
D6–D3 are reserved
D7 is disable (logic 1) bit
NOTES: A. D7 can be set to a logic 1 to disable the sense comparison function. At reset, the sense comparison is
enabled (D7 = logic 0). D6–D3 are reserved. If the sense-test register is written to disable the sense
comparator function, bits D6–D0 need to be set to a logic 0.
B. Both the SENSE output and the sense-test register are latched by the falling edge of the internally sampled
blank signal (SYSBL or VGABL depending on mode). In order to have stable voltage inputs to the
comparators, the frame-buffer inputs should be set up such that data entering the DACs remains
unchanged for a sufficient period of time prior to and after the blank-signal falling edge.
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