參數(shù)資料
型號(hào)： TVP3010-135
廠商： Texas Instruments, Inc.
英文描述： Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
中文描述： 硬件光標(biāo)，伽瑪校正貴賓（135MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板）
文件頁數(shù)： 25/100頁
文件大?。?/td> 571K
代理商： TVP3010-135
2–11
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
Blank
(internal signal
before dot clock
pipeline delay)
Pixel Data
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group of Pixel Data
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
First Group of Pixel Data
7th
Group
Last
Group
Latch Second Group
of Pixel Data
SCLK Between Split Shift-Register Transfer and Regular Shift-Register Transfer
SFLAG Input
Figure 2–5. SCLK/VCLK Control Timing
(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)
Multiplexing Scheme
The TVP3010 palette offers a highly versatile multiplexing scheme as illustrated in Tables 2–6 through 2–11.
The multiplexing scheme allows the pixel bus to be programmed to 1, 2, 4, 8, 12, 16, 24, or 32 bits/pixel with
pixel bus widths ranging from 1 bit to 32 bits. The use of on-chip multiplexing allows graphics systems to
be designed that can support multiple pixel depths and resolutions with no hardware modification. It also
allows the system to be configured to the amount of RAM available. For example, if only 256K bytes of
memory are available, an 800-by-600 mode with 4 bit planes (four bits per pixel) could be implemented using
an 8-bit-wide pixel bus. If at a later date another 256K bytes are added to another 8 bits of the pixel bus,
the user has the option of using 8 bit planes at the same resolution or 4 bit planes at a 1024-by-768
resolution. When a further 512K bytes are added to the remaining 16 bits of the pixel bus, the user has the
option of 8 bit planes at 1024-by-768 or 4 bit planes at 1280-by-1024. The TVP3010 palette can also be
configured for direct-color or true-color operation. All of the above could be achieved without any board-level
hardware modification and without any increase in the speed of the pixel bus.
2.4
Multiplexing of the pixel bus is controlled by and programmed through multiplex-control registers 1 and 2.
Table 2–6 details the multiplex-control register settings for each mode of operation (see also Sections 2.4.2
through 2.4.6).
2.4.1
The TVP3010 pixel bus supports both little- and big-endian data formats for all pseudo-color, direct-color,
and true-color modes of operation. The data-format select is controlled by general-control register bit 3 (see
Section 2.16.2). When general-control register (GCR) bit 3 is set to 0 (default), then the format is set to little
endian. When GCR bit 3 is set to 1, then the format is set to big endian.
Little-Endian and Big-Endian Data Format
In a big-endian design, the external VRAM data bus bits must be connected in reverse order to the VIP pixel
bus; i.e., D31 connected to P0, D0 connected to P31, etc. This ensures that the least significant channel
相關(guān)PDF資料
PDF描述
TVP3010-170 Hardware Cursor, GAMMA Correction VIP(170MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
TVP3010-85 Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
TVP3010C Video Interface Palette
TVP3010M Video Interface Palette
TVP3020-175 Video Interface PALETTE(視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3010-135FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3010-135MGA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3010-135MGAB 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3010-170FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3010-85FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
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