參數(shù)資料
型號(hào)： TVP3010-135
廠商： Texas Instruments, Inc.
英文描述： Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
中文描述： 硬件光標(biāo)，伽瑪校正貴賓（135MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板）
文件頁(yè)數(shù)： 84/100頁(yè)
文件大?。?/td> 571K
代理商： TVP3010-135
D–2
Table D–4. 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked, Overlay PSEL Switched
REGISTER
INDEX
(HEX)
SETTING
(HEX)
DESCRIPTION
Input-Clock Selection
1A
xx
Any clock can be chosen
Output-Clock Selection
1B
40
RCLK = SCLK = /1, VCLK = /1 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
0C
Self clocked, PSEL enabled, overlay when PSEL = 1
Color-Key Control
38
00
Disabled, pointing to nonpalette graphics
Multiplexer-Control Register 1
18
06
24-bit direct color
Multiplexer-Control Register 2
19
1B
24-bit direct color, 32-bit pixel bus width
Table D–5. 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Externally-Clocked, VGA PSEL Switched
REGISTER
INDEX
(HEX)
SETTING
(HEX)
DESCRIPTION
Input-Clock Selection
1A
xx
Any clock can be chosen
Output-Clock Selection
1B
40
RCLK = SCLK = /1, VCLK = /1 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
04
Externally clocked, PSEL enabled, VGA when PSEL = 1
Color-Key Control
38
00
Disabled, pointing to nonpalette graphics
Multiplexer-Control Register 1
18
06
24-bit direct color
Multiplexer-Control Register 2
19
9B
24-bit direct color, 32-bit pixel bus width
Configuration Register
1E
20
LCLK enabled for external timing mode
Table D–6. 16-Bit Direct Color (32-Bit Pixel Bus, 2:1) Self-Clocked,
Overlay Auxiliary Window Switched
REGISTER
INDEX
(HEX)
SETTING
(HEX)
DESCRIPTION
Input-Clock Selection
1A
xx
Any clock can be chosen
Output-Clock Selection
1B
49
RCLK = SCLK = /2, VCLK = /2 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
0A
Self clocked, auxiliary window enabled, overlay in window
Color-Key Control
38
00
Disabled, pointing to nonpalette graphics
Multiplexer-Control Register 1
18
05
16-bit direct color – XGA format
Multiplexer-Control Register 2
19
03
16-bit direct color, 32-bit pixel bus width
NOTE: For this mode, the auxiliary-window start and stop registers (Index 10–17) must be programmed with the
appropriate window coordinates (within active display). See sections 2.16.6 and 2.16.7.
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