參數(shù)資料
型號(hào): TVP3010-135
廠商: Texas Instruments, Inc.
英文描述: Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
中文描述: 硬件光標(biāo),伽瑪校正貴賓(135MHz,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
文件頁數(shù): 52/100頁
文件大?。?/td> 571K
代理商: TVP3010-135
2–38
2.16.2
The general-control register is used to control various functions of the TVP3010 palette. It can be accessed
by the MPU at any time. Bit 7 of the general-control register corresponds to data bus bit 7, index = 1D (hex).
General-Control Register
Table 2–13. General-Control Register
BIT
NAME
VALUES
DESCRIPTION
GCR7
0: External OVS terminal
(default)
Overscan-control select. Selects external terminal control or internally
generated overscan control See Section 2 7
1: Internal
GCR6
0: Disable (default)
Overscan enable. Specifies whether to enable the user-defined overscan
Overscan enable. Specifies whether to enable the user defined overscan
screen borders.
1: Enable
GCR5
0: Disable
Sync enable. This bit specifies whether SYNC information is to be output onto
IOG.
1: Enable (default)
GCR4
0: 0 IRE (default)
Pedestal control. This bit specifies whether a 0 or 7.5 IRE blanking pedestal
istobegeneratedonthevideooutputs 0IREspecifiesthattheblackandblank
isto be generated on the video outputs. 0 IRE specifies that the black and blank
levels are the same.
1: 7.5 IRE
GCR3
0: Little-endian (default)
Little-endian/big-endian select. Selects either little- or big-endian format for the
Little endian/big endian select. Selects either little or big endian format for the
pixel-bus frame-buffer interface. See Sections 2.4 and Appendix C.
1: Big-endian
GCR2
0: Disable (default)
Split shift-register-transfer enable See Section 2 15
Split shift-register-transfer enable. See Section 2.15.
1: Enable
GCR1
0: Active (low) (default)
VSYNCOUT output polarity See Section 2 14
VSYNCOUT output polarity. See Section 2.14.
1: Active (high)
GCR0
0: Active (low) (default)
1: Active (high)
HSYNCOUT output polarity See Section 2 14
HSYNCOUT output polarity. See Section 2.14.
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